xref: /llvm-project/llvm/test/CodeGen/WebAssembly/vector-sdiv.ll (revision 73856247eef35f5336e485dc009842a5b991c421)
1; RUN: llc < %s -asm-verbose=false -fast-isel=false -disable-wasm-fallthrough-return-opt | FileCheck %s
2
3target triple = "wasm32-unknown-unknown"
4
5; This should be treated as a non-splat vector of pow2 divisor, so sdivs will be
6; transformed to shrs in DAGCombiner. There will be 4 stores and 3 shrs (For '1'
7; entry we don't need a shr).
8
9; CHECK-LABEL: vector_sdiv:
10; CHECK-DAG:  i32.store
11; CHECK-DAG:  i32.shr_u
12; CHECK-DAG:  i32.store
13; CHECK-DAG:  i32.shr_u
14; CHECK-DAG:  i32.store
15; CHECK-DAG:  i32.shr_u
16; CHECK-DAG:  i32.store
17define void @vector_sdiv(ptr %x, ptr readonly %y) {
18entry:
19  %0 = load <4 x i32>, ptr %y, align 16
20  %div = sdiv <4 x i32> %0, <i32 1, i32 4, i32 2, i32 8>
21  store <4 x i32> %div, ptr %x, align 16
22  ret void
23}
24