xref: /llvm-project/llvm/test/CodeGen/WebAssembly/atomic-fence.ll (revision 122b0220fd45ee71acda912b0b712bb8edb6ba46)
1; RUN: llc < %s | FileCheck %s --check-prefix NOATOMIC
2; RUN: llc < %s -asm-verbose=false -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+atomics | FileCheck %s
3
4target triple = "wasm32-unknown-unknown"
5
6; A multithread fence is lowered to an atomic.fence instruction.
7; CHECK-LABEL: multithread_fence:
8; CHECK:  atomic.fence
9; NOATOMIC-NOT: i32.atomic.rmw.or
10define void @multithread_fence() {
11  fence seq_cst
12  ret void
13}
14
15; Fences with weaker memory orderings than seq_cst should be treated the same
16; because atomic memory access in wasm are sequentially consistent.
17; CHECK-LABEL: multithread_weak_fence:
18; CHECK:       atomic.fence
19; CHECK-NEXT:  atomic.fence
20; CHECK-NEXT:  atomic.fence
21define void @multithread_weak_fence() {
22  fence acquire
23  fence release
24  fence acq_rel
25  ret void
26}
27
28; A singlethread fence becomes compiler_fence instruction, a pseudo instruction
29; that acts as a compiler barrier. The barrier should not be emitted to .s file.
30; CHECK-LABEL: singlethread_fence:
31; CHECK-NOT: compiler_fence
32; CHECK-NOT: atomic_fence
33define void @singlethread_fence() {
34  fence syncscope("singlethread") seq_cst
35  fence syncscope("singlethread") acquire
36  fence syncscope("singlethread") release
37  fence syncscope("singlethread") acq_rel
38  ret void
39}
40