xref: /llvm-project/llvm/test/CodeGen/VE/Vector/vp_reduce_and.ll (revision 5240e0b891fc4bf69d362199f70c94c28a7b9465)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -O0 --mtriple=ve -mattr=+vpu | FileCheck %s
3
4declare i64 @llvm.vp.reduce.and.v256i64(i64, <256 x i64>, <256 x i1>, i32)
5
6define fastcc i64 @vp_reduce_and_v256i64(i64 %s, <256 x i64> %v, <256 x i1> %m, i32 %n) {
7; CHECK-LABEL: vp_reduce_and_v256i64:
8; CHECK:       # %bb.0:
9; CHECK-NEXT:    and %s1, %s1, (32)0
10; CHECK-NEXT:    # kill: def $sw1 killed $sw1 killed $sx1
11; CHECK-NEXT:    lvl %s1
12; CHECK-NEXT:    vrand %v0, %v0, %vm1
13; CHECK-NEXT:    lvs %s1, %v0(0)
14; CHECK-NEXT:    and %s0, %s0, %s1
15; CHECK-NEXT:    b.l.t (, %s10)
16  %r = call i64 @llvm.vp.reduce.and.v256i64(i64 %s, <256 x i64> %v, <256 x i1> %m, i32 %n)
17  ret i64 %r
18}
19
20declare i32 @llvm.vp.reduce.and.v256i32(i32, <256 x i32>, <256 x i1>, i32)
21
22define fastcc i32 @vp_reduce_and_v256i32(i32 %s, <256 x i32> %v, <256 x i1> %m, i32 %n) {
23; CHECK-LABEL: vp_reduce_and_v256i32:
24; CHECK:       # %bb.0:
25; CHECK-NEXT:    and %s2, %s0, (32)0
26; CHECK-NEXT:    # kill: def $sw2 killed $sw2 killed $sx2
27; CHECK-NEXT:    and %s1, %s1, (32)0
28; CHECK-NEXT:    # kill: def $sw1 killed $sw1 killed $sx1
29; CHECK-NEXT:    lvl %s1
30; CHECK-NEXT:    vrand %v0, %v0, %vm1
31; CHECK-NEXT:    lvs %s1, %v0(0)
32; CHECK-NEXT:    or %s2, 0, %s1
33; CHECK-NEXT:    # implicit-def: $sx1
34; CHECK-NEXT:    or %s1, 0, %s2
35; CHECK-NEXT:    and %s0, %s0, %s1
36; CHECK-NEXT:    b.l.t (, %s10)
37  %r = call i32 @llvm.vp.reduce.and.v256i32(i32 %s, <256 x i32> %v, <256 x i1> %m, i32 %n)
38  ret i32 %r
39}
40
41
42