xref: /llvm-project/llvm/test/CodeGen/VE/Vector/vp_merge.ll (revision 5240e0b891fc4bf69d362199f70c94c28a7b9465) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
3
4declare <256 x i32> @llvm.vp.merge.v256i32(<256 x i1>, <256 x i32>, <256 x i32>, i32)
5
6define fastcc <256 x i32> @test_vp_merge_v256i32_vv(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %pivot) {
7; CHECK-LABEL: test_vp_merge_v256i32_vv:
8; CHECK:       # %bb.0:
9; CHECK-NEXT:    and %s0, %s0, (32)0
10; CHECK-NEXT:    lvl %s0
11; CHECK-NEXT:    vmrg %v1, %v1, %v0, %vm1
12; CHECK-NEXT:    lea %s16, 256
13; CHECK-NEXT:    lvl %s16
14; CHECK-NEXT:    vor %v0, (0)1, %v1
15; CHECK-NEXT:    b.l.t (, %s10)
16  %r0 = call <256 x i32> @llvm.vp.merge.v256i32(<256 x i1> %m, <256 x i32> %i0, <256 x i32> %i1, i32 %pivot)
17  ret <256 x i32> %r0
18}
19
20define fastcc <256 x i32> @test_vp_merge_v256i32_vr(<256 x i32> %i0, i32 %s1, <256 x i1> %m, i32 %pivot) {
21; CHECK-LABEL: test_vp_merge_v256i32_vr:
22; CHECK:       # %bb.0:
23; CHECK-NEXT:    and %s1, %s1, (32)0
24; CHECK-NEXT:    and %s0, %s0, (32)0
25; CHECK-NEXT:    lea %s2, 256
26; CHECK-NEXT:    lvl %s2
27; CHECK-NEXT:    vbrd %v1, %s0
28; CHECK-NEXT:    lvl %s1
29; CHECK-NEXT:    vmrg %v1, %v1, %v0, %vm1
30; CHECK-NEXT:    lea %s16, 256
31; CHECK-NEXT:    lvl %s16
32; CHECK-NEXT:    vor %v0, (0)1, %v1
33; CHECK-NEXT:    b.l.t (, %s10)
34  %xins = insertelement <256 x i32> undef, i32 %s1, i32 0
35  %i1 = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
36  %r0 = call <256 x i32> @llvm.vp.merge.v256i32(<256 x i1> %m, <256 x i32> %i0, <256 x i32> %i1, i32 %pivot)
37  ret <256 x i32> %r0
38}
39
40declare <256 x float> @llvm.vp.merge.v256f32(<256 x i1>, <256 x float>, <256 x float>, i32)
41
42define fastcc <256 x float> @test_vp_merge_v256f32_vv(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %pivot) {
43; CHECK-LABEL: test_vp_merge_v256f32_vv:
44; CHECK:       # %bb.0:
45; CHECK-NEXT:    and %s0, %s0, (32)0
46; CHECK-NEXT:    lvl %s0
47; CHECK-NEXT:    vmrg %v1, %v1, %v0, %vm1
48; CHECK-NEXT:    lea %s16, 256
49; CHECK-NEXT:    lvl %s16
50; CHECK-NEXT:    vor %v0, (0)1, %v1
51; CHECK-NEXT:    b.l.t (, %s10)
52  %r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %i0, <256 x float> %i1, i32 %pivot)
53  ret <256 x float> %r0
54}
55
56define fastcc <256 x float> @test_vp_merge_v256f32_vr(<256 x float> %i0, float %s1, <256 x i1> %m, i32 %pivot) {
57; CHECK-LABEL: test_vp_merge_v256f32_vr:
58; CHECK:       # %bb.0:
59; CHECK-NEXT:    and %s1, %s1, (32)0
60; CHECK-NEXT:    lea %s2, 256
61; CHECK-NEXT:    lvl %s2
62; CHECK-NEXT:    vbrd %v1, %s0
63; CHECK-NEXT:    lvl %s1
64; CHECK-NEXT:    vmrg %v1, %v1, %v0, %vm1
65; CHECK-NEXT:    lea %s16, 256
66; CHECK-NEXT:    lvl %s16
67; CHECK-NEXT:    vor %v0, (0)1, %v1
68; CHECK-NEXT:    b.l.t (, %s10)
69  %xins = insertelement <256 x float> undef, float %s1, i32 0
70  %i1 = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
71  %r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %i0, <256 x float> %i1, i32 %pivot)
72  ret <256 x float> %r0
73}
74
75declare <256 x double> @llvm.vp.merge.v256f64(<256 x i1>, <256 x double>, <256 x double>, i32)
76
77define fastcc <256 x double> @test_vp_merge_v256f64_vv(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %pivot) {
78; CHECK-LABEL: test_vp_merge_v256f64_vv:
79; CHECK:       # %bb.0:
80; CHECK-NEXT:    and %s0, %s0, (32)0
81; CHECK-NEXT:    lvl %s0
82; CHECK-NEXT:    vmrg %v1, %v1, %v0, %vm1
83; CHECK-NEXT:    lea %s16, 256
84; CHECK-NEXT:    lvl %s16
85; CHECK-NEXT:    vor %v0, (0)1, %v1
86; CHECK-NEXT:    b.l.t (, %s10)
87  %r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %i0, <256 x double> %i1, i32 %pivot)
88  ret <256 x double> %r0
89}
90
91define fastcc <256 x double> @test_vp_merge_v256f64_vr(<256 x double> %i0, double %s1, <256 x i1> %m, i32 %pivot) {
92; CHECK-LABEL: test_vp_merge_v256f64_vr:
93; CHECK:       # %bb.0:
94; CHECK-NEXT:    and %s1, %s1, (32)0
95; CHECK-NEXT:    lea %s2, 256
96; CHECK-NEXT:    lvl %s2
97; CHECK-NEXT:    vbrd %v1, %s0
98; CHECK-NEXT:    lvl %s1
99; CHECK-NEXT:    vmrg %v1, %v1, %v0, %vm1
100; CHECK-NEXT:    lea %s16, 256
101; CHECK-NEXT:    lvl %s16
102; CHECK-NEXT:    vor %v0, (0)1, %v1
103; CHECK-NEXT:    b.l.t (, %s10)
104  %xins = insertelement <256 x double> undef, double %s1, i32 0
105  %i1 = shufflevector <256 x double> %xins, <256 x double> undef, <256 x i32> zeroinitializer
106  %r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %i0, <256 x double> %i1, i32 %pivot)
107  ret <256 x double> %r0
108}
109
110declare <256 x i64> @llvm.vp.merge.v256i64(<256 x i1>, <256 x i64>, <256 x i64>, i32)
111
112define fastcc <256 x i64> @test_vp_merge_v256i64_vv(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %pivot) {
113; CHECK-LABEL: test_vp_merge_v256i64_vv:
114; CHECK:       # %bb.0:
115; CHECK-NEXT:    and %s0, %s0, (32)0
116; CHECK-NEXT:    lvl %s0
117; CHECK-NEXT:    vmrg %v1, %v1, %v0, %vm1
118; CHECK-NEXT:    lea %s16, 256
119; CHECK-NEXT:    lvl %s16
120; CHECK-NEXT:    vor %v0, (0)1, %v1
121; CHECK-NEXT:    b.l.t (, %s10)
122  %r0 = call <256 x i64> @llvm.vp.merge.v256i64(<256 x i1> %m, <256 x i64> %i0, <256 x i64> %i1, i32 %pivot)
123  ret <256 x i64> %r0
124}
125
126define fastcc <256 x i64> @test_vp_merge_v256i64_vr(<256 x i64> %i0, i64 %s1, <256 x i1> %m, i32 %pivot) {
127; CHECK-LABEL: test_vp_merge_v256i64_vr:
128; CHECK:       # %bb.0:
129; CHECK-NEXT:    and %s1, %s1, (32)0
130; CHECK-NEXT:    lea %s2, 256
131; CHECK-NEXT:    lvl %s2
132; CHECK-NEXT:    vbrd %v1, %s0
133; CHECK-NEXT:    lvl %s1
134; CHECK-NEXT:    vmrg %v1, %v1, %v0, %vm1
135; CHECK-NEXT:    lea %s16, 256
136; CHECK-NEXT:    lvl %s16
137; CHECK-NEXT:    vor %v0, (0)1, %v1
138; CHECK-NEXT:    b.l.t (, %s10)
139  %xins = insertelement <256 x i64> undef, i64 %s1, i32 0
140  %i1 = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
141  %r0 = call <256 x i64> @llvm.vp.merge.v256i64(<256 x i1> %m, <256 x i64> %i0, <256 x i64> %i1, i32 %pivot)
142  ret <256 x i64> %r0
143}
144