xref: /llvm-project/llvm/test/CodeGen/VE/Vector/vp_add.ll (revision 5240e0b891fc4bf69d362199f70c94c28a7b9465)
1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
2
3declare <256 x i32> @llvm.vp.add.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
4
5define fastcc <256 x i32> @test_vp_add_v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n) {
6; CHECK-LABEL: test_vp_add_v256i32:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    and %s0, %s0, (32)0
9; CHECK-NEXT:    lvl %s0
10; CHECK-NEXT:    vadds.w.sx %v0, %v0, %v1, %vm1
11; CHECK-NEXT:    b.l.t (, %s10)
12  %r0 = call <256 x i32> @llvm.vp.add.v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n)
13  ret <256 x i32> %r0
14}
15
16
17declare <256 x i64> @llvm.vp.add.v256i64(<256 x i64>, <256 x i64>, <256 x i1>, i32)
18
19define fastcc <256 x i64> @test_vp_int_v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n) {
20; CHECK-LABEL: test_vp_int_v256i64:
21; CHECK:       # %bb.0:
22; CHECK-NEXT:    and %s0, %s0, (32)0
23; CHECK-NEXT:    lvl %s0
24; CHECK-NEXT:    vadds.l %v0, %v0, %v1, %vm1
25; CHECK-NEXT:    b.l.t (, %s10)
26  %r0 = call <256 x i64> @llvm.vp.add.v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n)
27  ret <256 x i64> %r0
28}
29
30