xref: /llvm-project/llvm/test/CodeGen/VE/Vector/vec_select.ll (revision 5240e0b891fc4bf69d362199f70c94c28a7b9465) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
3
4declare <256 x i32> @llvm.vec.select.v256i32(<256 x i1>, <256 x i32>, <256 x i32>, i32)
5
6define fastcc <256 x i32> @test_vec_select_v256i32_vv(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m) {
7; CHECK-LABEL: test_vec_select_v256i32_vv:
8; CHECK:       # %bb.0:
9; CHECK-NEXT:    lea %s0, 256
10; CHECK-NEXT:    lvl %s0
11; CHECK-NEXT:    vmrg %v1, %v1, %v0, %vm1
12; CHECK-NEXT:    lea %s16, 256
13; CHECK-NEXT:    lvl %s16
14; CHECK-NEXT:    vor %v0, (0)1, %v1
15; CHECK-NEXT:    b.l.t (, %s10)
16  %r0 = select <256 x i1> %m, <256 x i32> %i0, <256 x i32> %i1
17  ret <256 x i32> %r0
18}
19
20define fastcc <256 x i32> @test_vec_select_v256i32_vr(<256 x i32> %i0, i32 %s1, <256 x i1> %m) {
21; CHECK-LABEL: test_vec_select_v256i32_vr:
22; CHECK:       # %bb.0:
23; CHECK-NEXT:    and %s0, %s0, (32)0
24; CHECK-NEXT:    lea %s1, 256
25; CHECK-NEXT:    lvl %s1
26; CHECK-NEXT:    vbrd %v1, %s0
27; CHECK-NEXT:    vmrg %v1, %v1, %v0, %vm1
28; CHECK-NEXT:    lea %s16, 256
29; CHECK-NEXT:    lvl %s16
30; CHECK-NEXT:    vor %v0, (0)1, %v1
31; CHECK-NEXT:    b.l.t (, %s10)
32  %xins = insertelement <256 x i32> undef, i32 %s1, i32 0
33  %i1 = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
34  %r0 = select <256 x i1> %m, <256 x i32> %i0, <256 x i32> %i1
35  ret <256 x i32> %r0
36}
37
38declare <256 x float> @llvm.vec.select.v256f32(<256 x i1>, <256 x float>, <256 x float>, i32)
39
40define fastcc <256 x float> @test_vec_select_v256f32_vv(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m) {
41; CHECK-LABEL: test_vec_select_v256f32_vv:
42; CHECK:       # %bb.0:
43; CHECK-NEXT:    lea %s0, 256
44; CHECK-NEXT:    lvl %s0
45; CHECK-NEXT:    vmrg %v1, %v1, %v0, %vm1
46; CHECK-NEXT:    lea %s16, 256
47; CHECK-NEXT:    lvl %s16
48; CHECK-NEXT:    vor %v0, (0)1, %v1
49; CHECK-NEXT:    b.l.t (, %s10)
50  %r0 = select <256 x i1> %m, <256 x float> %i0, <256 x float> %i1
51  ret <256 x float> %r0
52}
53
54define fastcc <256 x float> @test_vec_select_v256f32_vr(<256 x float> %i0, float %s1, <256 x i1> %m) {
55; CHECK-LABEL: test_vec_select_v256f32_vr:
56; CHECK:       # %bb.0:
57; CHECK-NEXT:    lea %s1, 256
58; CHECK-NEXT:    lvl %s1
59; CHECK-NEXT:    vbrd %v1, %s0
60; CHECK-NEXT:    vmrg %v1, %v1, %v0, %vm1
61; CHECK-NEXT:    lea %s16, 256
62; CHECK-NEXT:    lvl %s16
63; CHECK-NEXT:    vor %v0, (0)1, %v1
64; CHECK-NEXT:    b.l.t (, %s10)
65  %xins = insertelement <256 x float> undef, float %s1, i32 0
66  %i1 = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
67  %r0 = select <256 x i1> %m, <256 x float> %i0, <256 x float> %i1
68  ret <256 x float> %r0
69}
70
71declare <256 x double> @llvm.vec.select.v256f64(<256 x i1>, <256 x double>, <256 x double>, i32)
72
73define fastcc <256 x double> @test_vec_select_v256f64_vv(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m) {
74; CHECK-LABEL: test_vec_select_v256f64_vv:
75; CHECK:       # %bb.0:
76; CHECK-NEXT:    lea %s0, 256
77; CHECK-NEXT:    lvl %s0
78; CHECK-NEXT:    vmrg %v1, %v1, %v0, %vm1
79; CHECK-NEXT:    lea %s16, 256
80; CHECK-NEXT:    lvl %s16
81; CHECK-NEXT:    vor %v0, (0)1, %v1
82; CHECK-NEXT:    b.l.t (, %s10)
83  %r0 = select <256 x i1> %m, <256 x double> %i0, <256 x double> %i1
84  ret <256 x double> %r0
85}
86
87define fastcc <256 x double> @test_vec_select_v256f64_vr(<256 x double> %i0, double %s1, <256 x i1> %m) {
88; CHECK-LABEL: test_vec_select_v256f64_vr:
89; CHECK:       # %bb.0:
90; CHECK-NEXT:    lea %s1, 256
91; CHECK-NEXT:    lvl %s1
92; CHECK-NEXT:    vbrd %v1, %s0
93; CHECK-NEXT:    vmrg %v1, %v1, %v0, %vm1
94; CHECK-NEXT:    lea %s16, 256
95; CHECK-NEXT:    lvl %s16
96; CHECK-NEXT:    vor %v0, (0)1, %v1
97; CHECK-NEXT:    b.l.t (, %s10)
98  %xins = insertelement <256 x double> undef, double %s1, i32 0
99  %i1 = shufflevector <256 x double> %xins, <256 x double> undef, <256 x i32> zeroinitializer
100  %r0 = select <256 x i1> %m, <256 x double> %i0, <256 x double> %i1
101  ret <256 x double> %r0
102}
103
104declare <256 x i64> @llvm.vec.select.v256i64(<256 x i1>, <256 x i64>, <256 x i64>, i32)
105
106define fastcc <256 x i64> @test_vec_select_v256i64_vv(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m) {
107; CHECK-LABEL: test_vec_select_v256i64_vv:
108; CHECK:       # %bb.0:
109; CHECK-NEXT:    lea %s0, 256
110; CHECK-NEXT:    lvl %s0
111; CHECK-NEXT:    vmrg %v1, %v1, %v0, %vm1
112; CHECK-NEXT:    lea %s16, 256
113; CHECK-NEXT:    lvl %s16
114; CHECK-NEXT:    vor %v0, (0)1, %v1
115; CHECK-NEXT:    b.l.t (, %s10)
116  %r0 = select <256 x i1> %m, <256 x i64> %i0, <256 x i64> %i1
117  ret <256 x i64> %r0
118}
119
120define fastcc <256 x i64> @test_vec_select_v256i64_vr(<256 x i64> %i0, i64 %s1, <256 x i1> %m) {
121; CHECK-LABEL: test_vec_select_v256i64_vr:
122; CHECK:       # %bb.0:
123; CHECK-NEXT:    lea %s1, 256
124; CHECK-NEXT:    lvl %s1
125; CHECK-NEXT:    vbrd %v1, %s0
126; CHECK-NEXT:    vmrg %v1, %v1, %v0, %vm1
127; CHECK-NEXT:    lea %s16, 256
128; CHECK-NEXT:    lvl %s16
129; CHECK-NEXT:    vor %v0, (0)1, %v1
130; CHECK-NEXT:    b.l.t (, %s10)
131  %xins = insertelement <256 x i64> undef, i64 %s1, i32 0
132  %i1 = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
133  %r0 = select <256 x i1> %m, <256 x i64> %i0, <256 x i64> %i1
134  ret <256 x i64> %r0
135}
136