xref: /llvm-project/llvm/test/CodeGen/VE/Vector/vec_load.ll (revision b006b60dc993b2e0ba3e412c80709477241b6be6) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=ve-unknown-unknown -mattr=+vpu | FileCheck %s
3
4declare <128 x double> @llvm.masked.load.v128f64.p0(ptr %0, i32 immarg %1, <128 x i1> %2, <128 x double> %3) #0
5
6; TODO: Custom widen by lowering to vvp_load in ReplaceNodeResult
7; Function Attrs: nounwind
8; define fastcc <128 x double> @vec_mload_v128f64(ptr %P, <128 x i1> %M) {
9;   %r = call <128 x double> @llvm.masked.load.v128f64.p0(ptr %P, i32 16, <128 x i1> %M, <128 x double> undef)
10;   ret <128 x double> %r
11; }
12
13
14declare <256 x double> @llvm.masked.load.v256f64.p0(ptr %0, i32 immarg %1, <256 x i1> %2, <256 x double> %3) #0
15
16; Function Attrs: nounwind
17define fastcc <256 x double> @vec_mload_v256f64(ptr %P, <256 x i1> %M) {
18; CHECK-LABEL: vec_mload_v256f64:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    lea %s1, 256
21; CHECK-NEXT:    lvl %s1
22; CHECK-NEXT:    vseq %v0
23; CHECK-NEXT:    vmulu.l %v0, 8, %v0, %vm1
24; CHECK-NEXT:    vaddu.l %v0, %s0, %v0, %vm1
25; CHECK-NEXT:    vgt %v0, %v0, 0, 0, %vm1
26; CHECK-NEXT:    b.l.t (, %s10)
27  %r = call <256 x double> @llvm.masked.load.v256f64.p0(ptr %P, i32 16, <256 x i1> %M, <256 x double> undef)
28  ret <256 x double> %r
29}
30
31; Function Attrs: nounwind
32define fastcc <256 x double> @vec_load_v256f64(ptr %P) {
33; CHECK-LABEL: vec_load_v256f64:
34; CHECK:       # %bb.0:
35; CHECK-NEXT:    lea %s1, 256
36; CHECK-NEXT:    lvl %s1
37; CHECK-NEXT:    vld %v0, 8, %s0
38; CHECK-NEXT:    b.l.t (, %s10)
39  %r = load <256 x double>, ptr %P, align 4
40  ret <256 x double> %r
41}
42
43; Function Attrs: nounwind
44define fastcc <256 x double> @vec_mload_pt_v256f64(ptr %P, <256 x double> %PT, <256 x i1> %M) {
45; CHECK-LABEL: vec_mload_pt_v256f64:
46; CHECK:       # %bb.0:
47; CHECK-NEXT:    lea %s1, 256
48; CHECK-NEXT:    lvl %s1
49; CHECK-NEXT:    vseq %v1
50; CHECK-NEXT:    vmulu.l %v1, 8, %v1, %vm1
51; CHECK-NEXT:    vaddu.l %v1, %s0, %v1, %vm1
52; CHECK-NEXT:    vgt %v1, %v1, 0, 0, %vm1
53; CHECK-NEXT:    vmrg %v0, %v0, %v1, %vm1
54; CHECK-NEXT:    b.l.t (, %s10)
55  %r = call <256 x double> @llvm.masked.load.v256f64.p0(ptr %P, i32 16, <256 x i1> %M, <256 x double> %PT)
56  ret <256 x double> %r
57}
58
59
60declare <256 x float> @llvm.masked.load.v256f32.p0(ptr %0, i32 immarg %1, <256 x i1> %2, <256 x float> %3) #0
61
62; Function Attrs: nounwind
63define fastcc <256 x float> @vec_mload_v256f32(ptr %P, <256 x i1> %M) {
64; CHECK-LABEL: vec_mload_v256f32:
65; CHECK:       # %bb.0:
66; CHECK-NEXT:    lea %s1, 256
67; CHECK-NEXT:    lvl %s1
68; CHECK-NEXT:    vseq %v0
69; CHECK-NEXT:    vmulu.l %v0, 4, %v0, %vm1
70; CHECK-NEXT:    vaddu.l %v0, %s0, %v0, %vm1
71; CHECK-NEXT:    vgtu %v0, %v0, 0, 0, %vm1
72; CHECK-NEXT:    b.l.t (, %s10)
73  %r = call <256 x float> @llvm.masked.load.v256f32.p0(ptr %P, i32 16, <256 x i1> %M, <256 x float> undef)
74  ret <256 x float> %r
75}
76
77; Function Attrs: nounwind
78define fastcc <256 x float> @vec_mload_pt_v256f32(ptr %P, <256 x float> %PT, <256 x i1> %M) {
79; CHECK-LABEL: vec_mload_pt_v256f32:
80; CHECK:       # %bb.0:
81; CHECK-NEXT:    lea %s1, 256
82; CHECK-NEXT:    lvl %s1
83; CHECK-NEXT:    vseq %v1
84; CHECK-NEXT:    vmulu.l %v1, 4, %v1, %vm1
85; CHECK-NEXT:    vaddu.l %v1, %s0, %v1, %vm1
86; CHECK-NEXT:    vgtu %v1, %v1, 0, 0, %vm1
87; CHECK-NEXT:    vmrg %v0, %v0, %v1, %vm1
88; CHECK-NEXT:    b.l.t (, %s10)
89  %r = call <256 x float> @llvm.masked.load.v256f32.p0(ptr %P, i32 16, <256 x i1> %M, <256 x float> %PT)
90  ret <256 x float> %r
91}
92
93
94declare <256 x i32> @llvm.masked.load.v256i32.p0(ptr %0, i32 immarg %1, <256 x i1> %2, <256 x i32> %3) #0
95
96; Function Attrs: nounwind
97define fastcc <256 x i32> @vec_mload_v256i32(ptr %P, <256 x i1> %M) {
98; CHECK-LABEL: vec_mload_v256i32:
99; CHECK:       # %bb.0:
100; CHECK-NEXT:    lea %s1, 256
101; CHECK-NEXT:    lvl %s1
102; CHECK-NEXT:    vseq %v0
103; CHECK-NEXT:    vmulu.l %v0, 4, %v0, %vm1
104; CHECK-NEXT:    vaddu.l %v0, %s0, %v0, %vm1
105; CHECK-NEXT:    vgtl.zx %v0, %v0, 0, 0, %vm1
106; CHECK-NEXT:    b.l.t (, %s10)
107  %r = call <256 x i32> @llvm.masked.load.v256i32.p0(ptr %P, i32 16, <256 x i1> %M, <256 x i32> undef)
108  ret <256 x i32> %r
109}
110
111; Function Attrs: nounwind
112define fastcc <256 x i32> @vec_mload_pt_v256i32(ptr %P, <256 x i32> %PT, <256 x i1> %M) {
113; CHECK-LABEL: vec_mload_pt_v256i32:
114; CHECK:       # %bb.0:
115; CHECK-NEXT:    lea %s1, 256
116; CHECK-NEXT:    lvl %s1
117; CHECK-NEXT:    vseq %v1
118; CHECK-NEXT:    vmulu.l %v1, 4, %v1, %vm1
119; CHECK-NEXT:    vaddu.l %v1, %s0, %v1, %vm1
120; CHECK-NEXT:    vgtl.zx %v1, %v1, 0, 0, %vm1
121; CHECK-NEXT:    vmrg %v0, %v0, %v1, %vm1
122; CHECK-NEXT:    b.l.t (, %s10)
123  %r = call <256 x i32> @llvm.masked.load.v256i32.p0(ptr %P, i32 16, <256 x i1> %M, <256 x i32> %PT)
124  ret <256 x i32> %r
125}
126
127attributes #0 = { argmemonly nounwind readonly willreturn }
128