xref: /llvm-project/llvm/test/CodeGen/VE/Vector/vec_icmp.ll (revision ae1bb44ed80b7b60c3fd2426c8bee3df93e4a314) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
3
4
5; <256 x i32>
6
7; Function Attrs: nounwind
8define fastcc <256 x i1> @icmp_sgt_vv_v256i32(<256 x i32> %x, <256 x i32> %y) {
9; CHECK-LABEL: icmp_sgt_vv_v256i32:
10; CHECK:       # %bb.0:
11; CHECK-NEXT:    lea %s0, 256
12; CHECK-NEXT:    lvl %s0
13; CHECK-NEXT:    vcmps.w.zx %v0, %v0, %v1
14; CHECK-NEXT:    vfmk.w.gt %vm1, %v0
15; CHECK-NEXT:    b.l.t (, %s10)
16  %z = icmp sgt <256 x i32> %x, %y
17  ret <256 x i1> %z
18}
19
20; Function Attrs: nounwind
21define fastcc <256 x i1> @icmp_sgt_sv_v256i32(i32 %x, <256 x i32> %y) {
22; CHECK-LABEL: icmp_sgt_sv_v256i32:
23; CHECK:       # %bb.0:
24; CHECK-NEXT:    and %s0, %s0, (32)0
25; CHECK-NEXT:    lea %s1, 256
26; CHECK-NEXT:    lvl %s1
27; CHECK-NEXT:    vbrd %v1, %s0
28; CHECK-NEXT:    vcmps.w.zx %v0, %v1, %v0
29; CHECK-NEXT:    vfmk.w.gt %vm1, %v0
30; CHECK-NEXT:    b.l.t (, %s10)
31  %xins = insertelement <256 x i32> undef, i32 %x, i32 0
32  %vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
33  %z = icmp sgt <256 x i32> %vx, %y
34  ret <256 x i1> %z
35}
36
37; Function Attrs: nounwind
38define fastcc <256 x i1> @icmp_sgt_vs_v256i32(<256 x i32> %x, i32 %y) {
39; CHECK-LABEL: icmp_sgt_vs_v256i32:
40; CHECK:       # %bb.0:
41; CHECK-NEXT:    and %s0, %s0, (32)0
42; CHECK-NEXT:    lea %s1, 256
43; CHECK-NEXT:    lvl %s1
44; CHECK-NEXT:    vbrd %v1, %s0
45; CHECK-NEXT:    vcmps.w.zx %v0, %v0, %v1
46; CHECK-NEXT:    vfmk.w.gt %vm1, %v0
47; CHECK-NEXT:    b.l.t (, %s10)
48  %yins = insertelement <256 x i32> undef, i32 %y, i32 0
49  %vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer
50  %z = icmp sgt <256 x i32> %x, %vy
51  ret <256 x i1> %z
52}
53
54; Function Attrs: nounwind
55define fastcc <256 x i1> @icmp_sge_vv_v256i32(<256 x i32> %x, <256 x i32> %y) {
56; CHECK-LABEL: icmp_sge_vv_v256i32:
57; CHECK:       # %bb.0:
58; CHECK-NEXT:    lea %s0, 256
59; CHECK-NEXT:    lvl %s0
60; CHECK-NEXT:    vcmps.w.zx %v0, %v0, %v1
61; CHECK-NEXT:    vfmk.w.ge %vm1, %v0
62; CHECK-NEXT:    b.l.t (, %s10)
63  %z = icmp sge <256 x i32> %x, %y
64  ret <256 x i1> %z
65}
66
67; Function Attrs: nounwind
68define fastcc <256 x i1> @icmp_sge_sv_v256i32(i32 %x, <256 x i32> %y) {
69; CHECK-LABEL: icmp_sge_sv_v256i32:
70; CHECK:       # %bb.0:
71; CHECK-NEXT:    and %s0, %s0, (32)0
72; CHECK-NEXT:    lea %s1, 256
73; CHECK-NEXT:    lvl %s1
74; CHECK-NEXT:    vbrd %v1, %s0
75; CHECK-NEXT:    vcmps.w.zx %v0, %v1, %v0
76; CHECK-NEXT:    vfmk.w.ge %vm1, %v0
77; CHECK-NEXT:    b.l.t (, %s10)
78  %xins = insertelement <256 x i32> undef, i32 %x, i32 0
79  %vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
80  %z = icmp sge <256 x i32> %vx, %y
81  ret <256 x i1> %z
82}
83
84; Function Attrs: nounwind
85define fastcc <256 x i1> @icmp_sge_vs_v256i32(<256 x i32> %x, i32 %y) {
86; CHECK-LABEL: icmp_sge_vs_v256i32:
87; CHECK:       # %bb.0:
88; CHECK-NEXT:    and %s0, %s0, (32)0
89; CHECK-NEXT:    lea %s1, 256
90; CHECK-NEXT:    lvl %s1
91; CHECK-NEXT:    vbrd %v1, %s0
92; CHECK-NEXT:    vcmps.w.zx %v0, %v0, %v1
93; CHECK-NEXT:    vfmk.w.ge %vm1, %v0
94; CHECK-NEXT:    b.l.t (, %s10)
95  %yins = insertelement <256 x i32> undef, i32 %y, i32 0
96  %vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer
97  %z = icmp sge <256 x i32> %x, %vy
98  ret <256 x i1> %z
99}
100
101; Function Attrs: nounwind
102define fastcc <256 x i1> @icmp_eq_vv_v256i32(<256 x i32> %x, <256 x i32> %y) {
103; CHECK-LABEL: icmp_eq_vv_v256i32:
104; CHECK:       # %bb.0:
105; CHECK-NEXT:    lea %s0, 256
106; CHECK-NEXT:    lvl %s0
107; CHECK-NEXT:    vcmpu.w %v0, %v0, %v1
108; CHECK-NEXT:    vfmk.w.eq %vm1, %v0
109; CHECK-NEXT:    b.l.t (, %s10)
110  %z = icmp eq <256 x i32> %x, %y
111  ret <256 x i1> %z
112}
113
114; Function Attrs: nounwind
115define fastcc <256 x i1> @icmp_eq_sv_v256i32(i32 %x, <256 x i32> %y) {
116; CHECK-LABEL: icmp_eq_sv_v256i32:
117; CHECK:       # %bb.0:
118; CHECK-NEXT:    and %s0, %s0, (32)0
119; CHECK-NEXT:    lea %s1, 256
120; CHECK-NEXT:    lvl %s1
121; CHECK-NEXT:    vbrd %v1, %s0
122; CHECK-NEXT:    vcmpu.w %v0, %v1, %v0
123; CHECK-NEXT:    vfmk.w.eq %vm1, %v0
124; CHECK-NEXT:    b.l.t (, %s10)
125  %xins = insertelement <256 x i32> undef, i32 %x, i32 0
126  %vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
127  %z = icmp eq <256 x i32> %vx, %y
128  ret <256 x i1> %z
129}
130
131; Function Attrs: nounwind
132define fastcc <256 x i1> @icmp_eq_vs_v256i32(<256 x i32> %x, i32 %y) {
133; CHECK-LABEL: icmp_eq_vs_v256i32:
134; CHECK:       # %bb.0:
135; CHECK-NEXT:    and %s0, %s0, (32)0
136; CHECK-NEXT:    lea %s1, 256
137; CHECK-NEXT:    lvl %s1
138; CHECK-NEXT:    vbrd %v1, %s0
139; CHECK-NEXT:    vcmpu.w %v0, %v0, %v1
140; CHECK-NEXT:    vfmk.w.eq %vm1, %v0
141; CHECK-NEXT:    b.l.t (, %s10)
142  %yins = insertelement <256 x i32> undef, i32 %y, i32 0
143  %vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer
144  %z = icmp eq <256 x i32> %x, %vy
145  ret <256 x i1> %z
146}
147
148; Function Attrs: nounwind
149define fastcc <256 x i1> @icmp_ne_vv_v256i32(<256 x i32> %x, <256 x i32> %y) {
150; CHECK-LABEL: icmp_ne_vv_v256i32:
151; CHECK:       # %bb.0:
152; CHECK-NEXT:    lea %s0, 256
153; CHECK-NEXT:    lvl %s0
154; CHECK-NEXT:    vcmpu.w %v0, %v0, %v1
155; CHECK-NEXT:    vfmk.w.ne %vm1, %v0
156; CHECK-NEXT:    b.l.t (, %s10)
157  %z = icmp ne <256 x i32> %x, %y
158  ret <256 x i1> %z
159}
160
161; Function Attrs: nounwind
162define fastcc <256 x i1> @icmp_ne_sv_v256i32(i32 %x, <256 x i32> %y) {
163; CHECK-LABEL: icmp_ne_sv_v256i32:
164; CHECK:       # %bb.0:
165; CHECK-NEXT:    and %s0, %s0, (32)0
166; CHECK-NEXT:    lea %s1, 256
167; CHECK-NEXT:    lvl %s1
168; CHECK-NEXT:    vbrd %v1, %s0
169; CHECK-NEXT:    vcmpu.w %v0, %v1, %v0
170; CHECK-NEXT:    vfmk.w.ne %vm1, %v0
171; CHECK-NEXT:    b.l.t (, %s10)
172  %xins = insertelement <256 x i32> undef, i32 %x, i32 0
173  %vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
174  %z = icmp ne <256 x i32> %vx, %y
175  ret <256 x i1> %z
176}
177
178; Function Attrs: nounwind
179define fastcc <256 x i1> @icmp_ne_vs_v256i32(<256 x i32> %x, i32 %y) {
180; CHECK-LABEL: icmp_ne_vs_v256i32:
181; CHECK:       # %bb.0:
182; CHECK-NEXT:    and %s0, %s0, (32)0
183; CHECK-NEXT:    lea %s1, 256
184; CHECK-NEXT:    lvl %s1
185; CHECK-NEXT:    vbrd %v1, %s0
186; CHECK-NEXT:    vcmpu.w %v0, %v0, %v1
187; CHECK-NEXT:    vfmk.w.ne %vm1, %v0
188; CHECK-NEXT:    b.l.t (, %s10)
189  %yins = insertelement <256 x i32> undef, i32 %y, i32 0
190  %vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer
191  %z = icmp ne <256 x i32> %x, %vy
192  ret <256 x i1> %z
193}
194
195; Function Attrs: nounwind
196define fastcc <256 x i1> @icmp_sle_vv_v256i32(<256 x i32> %x, <256 x i32> %y) {
197; CHECK-LABEL: icmp_sle_vv_v256i32:
198; CHECK:       # %bb.0:
199; CHECK-NEXT:    lea %s0, 256
200; CHECK-NEXT:    lvl %s0
201; CHECK-NEXT:    vcmps.w.zx %v0, %v0, %v1
202; CHECK-NEXT:    vfmk.w.le %vm1, %v0
203; CHECK-NEXT:    b.l.t (, %s10)
204  %z = icmp sle <256 x i32> %x, %y
205  ret <256 x i1> %z
206}
207
208; Function Attrs: nounwind
209define fastcc <256 x i1> @icmp_sle_sv_v256i32(i32 %x, <256 x i32> %y) {
210; CHECK-LABEL: icmp_sle_sv_v256i32:
211; CHECK:       # %bb.0:
212; CHECK-NEXT:    and %s0, %s0, (32)0
213; CHECK-NEXT:    lea %s1, 256
214; CHECK-NEXT:    lvl %s1
215; CHECK-NEXT:    vbrd %v1, %s0
216; CHECK-NEXT:    vcmps.w.zx %v0, %v1, %v0
217; CHECK-NEXT:    vfmk.w.le %vm1, %v0
218; CHECK-NEXT:    b.l.t (, %s10)
219  %xins = insertelement <256 x i32> undef, i32 %x, i32 0
220  %vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
221  %z = icmp sle <256 x i32> %vx, %y
222  ret <256 x i1> %z
223}
224
225; Function Attrs: nounwind
226define fastcc <256 x i1> @icmp_sle_vs_v256i32(<256 x i32> %x, i32 %y) {
227; CHECK-LABEL: icmp_sle_vs_v256i32:
228; CHECK:       # %bb.0:
229; CHECK-NEXT:    and %s0, %s0, (32)0
230; CHECK-NEXT:    lea %s1, 256
231; CHECK-NEXT:    lvl %s1
232; CHECK-NEXT:    vbrd %v1, %s0
233; CHECK-NEXT:    vcmps.w.zx %v0, %v0, %v1
234; CHECK-NEXT:    vfmk.w.le %vm1, %v0
235; CHECK-NEXT:    b.l.t (, %s10)
236  %yins = insertelement <256 x i32> undef, i32 %y, i32 0
237  %vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer
238  %z = icmp sle <256 x i32> %x, %vy
239  ret <256 x i1> %z
240}
241
242; Function Attrs: nounwind
243define fastcc <256 x i1> @icmp_slt_vv_v256i32(<256 x i32> %x, <256 x i32> %y) {
244; CHECK-LABEL: icmp_slt_vv_v256i32:
245; CHECK:       # %bb.0:
246; CHECK-NEXT:    lea %s0, 256
247; CHECK-NEXT:    lvl %s0
248; CHECK-NEXT:    vcmps.w.zx %v0, %v0, %v1
249; CHECK-NEXT:    vfmk.w.lt %vm1, %v0
250; CHECK-NEXT:    b.l.t (, %s10)
251  %z = icmp slt <256 x i32> %x, %y
252  ret <256 x i1> %z
253}
254
255; Function Attrs: nounwind
256define fastcc <256 x i1> @icmp_slt_sv_v256i32(i32 %x, <256 x i32> %y) {
257; CHECK-LABEL: icmp_slt_sv_v256i32:
258; CHECK:       # %bb.0:
259; CHECK-NEXT:    and %s0, %s0, (32)0
260; CHECK-NEXT:    lea %s1, 256
261; CHECK-NEXT:    lvl %s1
262; CHECK-NEXT:    vbrd %v1, %s0
263; CHECK-NEXT:    vcmps.w.zx %v0, %v1, %v0
264; CHECK-NEXT:    vfmk.w.lt %vm1, %v0
265; CHECK-NEXT:    b.l.t (, %s10)
266  %xins = insertelement <256 x i32> undef, i32 %x, i32 0
267  %vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
268  %z = icmp slt <256 x i32> %vx, %y
269  ret <256 x i1> %z
270}
271
272; Function Attrs: nounwind
273define fastcc <256 x i1> @icmp_slt_vs_v256i32(<256 x i32> %x, i32 %y) {
274; CHECK-LABEL: icmp_slt_vs_v256i32:
275; CHECK:       # %bb.0:
276; CHECK-NEXT:    and %s0, %s0, (32)0
277; CHECK-NEXT:    lea %s1, 256
278; CHECK-NEXT:    lvl %s1
279; CHECK-NEXT:    vbrd %v1, %s0
280; CHECK-NEXT:    vcmps.w.zx %v0, %v0, %v1
281; CHECK-NEXT:    vfmk.w.lt %vm1, %v0
282; CHECK-NEXT:    b.l.t (, %s10)
283  %yins = insertelement <256 x i32> undef, i32 %y, i32 0
284  %vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer
285  %z = icmp slt <256 x i32> %x, %vy
286  ret <256 x i1> %z
287}
288
289
290
291
292; Function Attrs: nounwind
293define fastcc <256 x i1> @icmp_ugt_vv_v256i32(<256 x i32> %x, <256 x i32> %y) {
294; CHECK-LABEL: icmp_ugt_vv_v256i32:
295; CHECK:       # %bb.0:
296; CHECK-NEXT:    lea %s0, 256
297; CHECK-NEXT:    lvl %s0
298; CHECK-NEXT:    vcmpu.w %v0, %v0, %v1
299; CHECK-NEXT:    vfmk.w.gt %vm1, %v0
300; CHECK-NEXT:    b.l.t (, %s10)
301  %z = icmp ugt <256 x i32> %x, %y
302  ret <256 x i1> %z
303}
304
305; Function Attrs: nounwind
306define fastcc <256 x i1> @icmp_ugt_sv_v256i32(i32 %x, <256 x i32> %y) {
307; CHECK-LABEL: icmp_ugt_sv_v256i32:
308; CHECK:       # %bb.0:
309; CHECK-NEXT:    and %s0, %s0, (32)0
310; CHECK-NEXT:    lea %s1, 256
311; CHECK-NEXT:    lvl %s1
312; CHECK-NEXT:    vbrd %v1, %s0
313; CHECK-NEXT:    vcmpu.w %v0, %v1, %v0
314; CHECK-NEXT:    vfmk.w.gt %vm1, %v0
315; CHECK-NEXT:    b.l.t (, %s10)
316  %xins = insertelement <256 x i32> undef, i32 %x, i32 0
317  %vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
318  %z = icmp ugt <256 x i32> %vx, %y
319  ret <256 x i1> %z
320}
321
322; Function Attrs: nounwind
323define fastcc <256 x i1> @icmp_ugt_vs_v256i32(<256 x i32> %x, i32 %y) {
324; CHECK-LABEL: icmp_ugt_vs_v256i32:
325; CHECK:       # %bb.0:
326; CHECK-NEXT:    and %s0, %s0, (32)0
327; CHECK-NEXT:    lea %s1, 256
328; CHECK-NEXT:    lvl %s1
329; CHECK-NEXT:    vbrd %v1, %s0
330; CHECK-NEXT:    vcmpu.w %v0, %v0, %v1
331; CHECK-NEXT:    vfmk.w.gt %vm1, %v0
332; CHECK-NEXT:    b.l.t (, %s10)
333  %yins = insertelement <256 x i32> undef, i32 %y, i32 0
334  %vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer
335  %z = icmp ugt <256 x i32> %x, %vy
336  ret <256 x i1> %z
337}
338
339; Function Attrs: nounwind
340define fastcc <256 x i1> @icmp_uge_vv_v256i32(<256 x i32> %x, <256 x i32> %y) {
341; CHECK-LABEL: icmp_uge_vv_v256i32:
342; CHECK:       # %bb.0:
343; CHECK-NEXT:    lea %s0, 256
344; CHECK-NEXT:    lvl %s0
345; CHECK-NEXT:    vcmpu.w %v0, %v0, %v1
346; CHECK-NEXT:    vfmk.w.ge %vm1, %v0
347; CHECK-NEXT:    b.l.t (, %s10)
348  %z = icmp uge <256 x i32> %x, %y
349  ret <256 x i1> %z
350}
351
352; Function Attrs: nounwind
353define fastcc <256 x i1> @icmp_uge_sv_v256i32(i32 %x, <256 x i32> %y) {
354; CHECK-LABEL: icmp_uge_sv_v256i32:
355; CHECK:       # %bb.0:
356; CHECK-NEXT:    and %s0, %s0, (32)0
357; CHECK-NEXT:    lea %s1, 256
358; CHECK-NEXT:    lvl %s1
359; CHECK-NEXT:    vbrd %v1, %s0
360; CHECK-NEXT:    vcmpu.w %v0, %v1, %v0
361; CHECK-NEXT:    vfmk.w.ge %vm1, %v0
362; CHECK-NEXT:    b.l.t (, %s10)
363  %xins = insertelement <256 x i32> undef, i32 %x, i32 0
364  %vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
365  %z = icmp uge <256 x i32> %vx, %y
366  ret <256 x i1> %z
367}
368
369; Function Attrs: nounwind
370define fastcc <256 x i1> @icmp_uge_vs_v256i32(<256 x i32> %x, i32 %y) {
371; CHECK-LABEL: icmp_uge_vs_v256i32:
372; CHECK:       # %bb.0:
373; CHECK-NEXT:    and %s0, %s0, (32)0
374; CHECK-NEXT:    lea %s1, 256
375; CHECK-NEXT:    lvl %s1
376; CHECK-NEXT:    vbrd %v1, %s0
377; CHECK-NEXT:    vcmpu.w %v0, %v0, %v1
378; CHECK-NEXT:    vfmk.w.ge %vm1, %v0
379; CHECK-NEXT:    b.l.t (, %s10)
380  %yins = insertelement <256 x i32> undef, i32 %y, i32 0
381  %vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer
382  %z = icmp uge <256 x i32> %x, %vy
383  ret <256 x i1> %z
384}
385
386; Function Attrs: nounwind
387define fastcc <256 x i1> @icmp_ule_vv_v256i32(<256 x i32> %x, <256 x i32> %y) {
388; CHECK-LABEL: icmp_ule_vv_v256i32:
389; CHECK:       # %bb.0:
390; CHECK-NEXT:    lea %s0, 256
391; CHECK-NEXT:    lvl %s0
392; CHECK-NEXT:    vcmpu.w %v0, %v0, %v1
393; CHECK-NEXT:    vfmk.w.le %vm1, %v0
394; CHECK-NEXT:    b.l.t (, %s10)
395  %z = icmp ule <256 x i32> %x, %y
396  ret <256 x i1> %z
397}
398
399; Function Attrs: nounwind
400define fastcc <256 x i1> @icmp_ule_sv_v256i32(i32 %x, <256 x i32> %y) {
401; CHECK-LABEL: icmp_ule_sv_v256i32:
402; CHECK:       # %bb.0:
403; CHECK-NEXT:    and %s0, %s0, (32)0
404; CHECK-NEXT:    lea %s1, 256
405; CHECK-NEXT:    lvl %s1
406; CHECK-NEXT:    vbrd %v1, %s0
407; CHECK-NEXT:    vcmpu.w %v0, %v1, %v0
408; CHECK-NEXT:    vfmk.w.le %vm1, %v0
409; CHECK-NEXT:    b.l.t (, %s10)
410  %xins = insertelement <256 x i32> undef, i32 %x, i32 0
411  %vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
412  %z = icmp ule <256 x i32> %vx, %y
413  ret <256 x i1> %z
414}
415
416; Function Attrs: nounwind
417define fastcc <256 x i1> @icmp_ule_vs_v256i32(<256 x i32> %x, i32 %y) {
418; CHECK-LABEL: icmp_ule_vs_v256i32:
419; CHECK:       # %bb.0:
420; CHECK-NEXT:    and %s0, %s0, (32)0
421; CHECK-NEXT:    lea %s1, 256
422; CHECK-NEXT:    lvl %s1
423; CHECK-NEXT:    vbrd %v1, %s0
424; CHECK-NEXT:    vcmpu.w %v0, %v0, %v1
425; CHECK-NEXT:    vfmk.w.le %vm1, %v0
426; CHECK-NEXT:    b.l.t (, %s10)
427  %yins = insertelement <256 x i32> undef, i32 %y, i32 0
428  %vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer
429  %z = icmp ule <256 x i32> %x, %vy
430  ret <256 x i1> %z
431}
432
433; Function Attrs: nounwind
434define fastcc <256 x i1> @icmp_ult_vv_v256i32(<256 x i32> %x, <256 x i32> %y) {
435; CHECK-LABEL: icmp_ult_vv_v256i32:
436; CHECK:       # %bb.0:
437; CHECK-NEXT:    lea %s0, 256
438; CHECK-NEXT:    lvl %s0
439; CHECK-NEXT:    vcmpu.w %v0, %v0, %v1
440; CHECK-NEXT:    vfmk.w.lt %vm1, %v0
441; CHECK-NEXT:    b.l.t (, %s10)
442  %z = icmp ult <256 x i32> %x, %y
443  ret <256 x i1> %z
444}
445
446; Function Attrs: nounwind
447define fastcc <256 x i1> @icmp_ult_sv_v256i32(i32 %x, <256 x i32> %y) {
448; CHECK-LABEL: icmp_ult_sv_v256i32:
449; CHECK:       # %bb.0:
450; CHECK-NEXT:    and %s0, %s0, (32)0
451; CHECK-NEXT:    lea %s1, 256
452; CHECK-NEXT:    lvl %s1
453; CHECK-NEXT:    vbrd %v1, %s0
454; CHECK-NEXT:    vcmpu.w %v0, %v1, %v0
455; CHECK-NEXT:    vfmk.w.lt %vm1, %v0
456; CHECK-NEXT:    b.l.t (, %s10)
457  %xins = insertelement <256 x i32> undef, i32 %x, i32 0
458  %vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
459  %z = icmp ult <256 x i32> %vx, %y
460  ret <256 x i1> %z
461}
462
463; Function Attrs: nounwind
464define fastcc <256 x i1> @icmp_ult_vs_v256i32(<256 x i32> %x, i32 %y) {
465; CHECK-LABEL: icmp_ult_vs_v256i32:
466; CHECK:       # %bb.0:
467; CHECK-NEXT:    and %s0, %s0, (32)0
468; CHECK-NEXT:    lea %s1, 256
469; CHECK-NEXT:    lvl %s1
470; CHECK-NEXT:    vbrd %v1, %s0
471; CHECK-NEXT:    vcmpu.w %v0, %v0, %v1
472; CHECK-NEXT:    vfmk.w.lt %vm1, %v0
473; CHECK-NEXT:    b.l.t (, %s10)
474  %yins = insertelement <256 x i32> undef, i32 %y, i32 0
475  %vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer
476  %z = icmp ult <256 x i32> %x, %vy
477  ret <256 x i1> %z
478}
479
480
481
482; <256 x i64>
483
484; Function Attrs: nounwind
485define fastcc <256 x i1> @icmp_sgt_vv_v256i64(<256 x i64> %x, <256 x i64> %y) {
486; CHECK-LABEL: icmp_sgt_vv_v256i64:
487; CHECK:       # %bb.0:
488; CHECK-NEXT:    lea %s0, 256
489; CHECK-NEXT:    lvl %s0
490; CHECK-NEXT:    vcmps.l %v0, %v0, %v1
491; CHECK-NEXT:    vfmk.l.gt %vm1, %v0
492; CHECK-NEXT:    b.l.t (, %s10)
493  %z = icmp sgt <256 x i64> %x, %y
494  ret <256 x i1> %z
495}
496
497; Function Attrs: nounwind
498define fastcc <256 x i1> @icmp_sgt_sv_v256i64(i64 %x, <256 x i64> %y) {
499; CHECK-LABEL: icmp_sgt_sv_v256i64:
500; CHECK:       # %bb.0:
501; CHECK-NEXT:    lea %s1, 256
502; CHECK-NEXT:    lvl %s1
503; CHECK-NEXT:    vbrd %v1, %s0
504; CHECK-NEXT:    vcmps.l %v0, %v1, %v0
505; CHECK-NEXT:    vfmk.l.gt %vm1, %v0
506; CHECK-NEXT:    b.l.t (, %s10)
507  %xins = insertelement <256 x i64> undef, i64 %x, i32 0
508  %vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
509  %z = icmp sgt <256 x i64> %vx, %y
510  ret <256 x i1> %z
511}
512
513; Function Attrs: nounwind
514define fastcc <256 x i1> @icmp_sgt_vs_v256i64(<256 x i64> %x, i64 %y) {
515; CHECK-LABEL: icmp_sgt_vs_v256i64:
516; CHECK:       # %bb.0:
517; CHECK-NEXT:    lea %s1, 256
518; CHECK-NEXT:    lvl %s1
519; CHECK-NEXT:    vbrd %v1, %s0
520; CHECK-NEXT:    vcmps.l %v0, %v0, %v1
521; CHECK-NEXT:    vfmk.l.gt %vm1, %v0
522; CHECK-NEXT:    b.l.t (, %s10)
523  %yins = insertelement <256 x i64> undef, i64 %y, i32 0
524  %vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer
525  %z = icmp sgt <256 x i64> %x, %vy
526  ret <256 x i1> %z
527}
528
529; Function Attrs: nounwind
530define fastcc <256 x i1> @icmp_sge_vv_v256i64(<256 x i64> %x, <256 x i64> %y) {
531; CHECK-LABEL: icmp_sge_vv_v256i64:
532; CHECK:       # %bb.0:
533; CHECK-NEXT:    lea %s0, 256
534; CHECK-NEXT:    lvl %s0
535; CHECK-NEXT:    vcmps.l %v0, %v0, %v1
536; CHECK-NEXT:    vfmk.l.ge %vm1, %v0
537; CHECK-NEXT:    b.l.t (, %s10)
538  %z = icmp sge <256 x i64> %x, %y
539  ret <256 x i1> %z
540}
541
542; Function Attrs: nounwind
543define fastcc <256 x i1> @icmp_sge_sv_v256i64(i64 %x, <256 x i64> %y) {
544; CHECK-LABEL: icmp_sge_sv_v256i64:
545; CHECK:       # %bb.0:
546; CHECK-NEXT:    lea %s1, 256
547; CHECK-NEXT:    lvl %s1
548; CHECK-NEXT:    vbrd %v1, %s0
549; CHECK-NEXT:    vcmps.l %v0, %v1, %v0
550; CHECK-NEXT:    vfmk.l.ge %vm1, %v0
551; CHECK-NEXT:    b.l.t (, %s10)
552  %xins = insertelement <256 x i64> undef, i64 %x, i32 0
553  %vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
554  %z = icmp sge <256 x i64> %vx, %y
555  ret <256 x i1> %z
556}
557
558; Function Attrs: nounwind
559define fastcc <256 x i1> @icmp_sge_vs_v256i64(<256 x i64> %x, i64 %y) {
560; CHECK-LABEL: icmp_sge_vs_v256i64:
561; CHECK:       # %bb.0:
562; CHECK-NEXT:    lea %s1, 256
563; CHECK-NEXT:    lvl %s1
564; CHECK-NEXT:    vbrd %v1, %s0
565; CHECK-NEXT:    vcmps.l %v0, %v0, %v1
566; CHECK-NEXT:    vfmk.l.ge %vm1, %v0
567; CHECK-NEXT:    b.l.t (, %s10)
568  %yins = insertelement <256 x i64> undef, i64 %y, i32 0
569  %vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer
570  %z = icmp sge <256 x i64> %x, %vy
571  ret <256 x i1> %z
572}
573
574; Function Attrs: nounwind
575define fastcc <256 x i1> @icmp_eq_vv_v256i64(<256 x i64> %x, <256 x i64> %y) {
576; CHECK-LABEL: icmp_eq_vv_v256i64:
577; CHECK:       # %bb.0:
578; CHECK-NEXT:    lea %s0, 256
579; CHECK-NEXT:    lvl %s0
580; CHECK-NEXT:    vcmpu.l %v0, %v0, %v1
581; CHECK-NEXT:    vfmk.l.eq %vm1, %v0
582; CHECK-NEXT:    b.l.t (, %s10)
583  %z = icmp eq <256 x i64> %x, %y
584  ret <256 x i1> %z
585}
586
587; Function Attrs: nounwind
588define fastcc <256 x i1> @icmp_eq_sv_v256i64(i64 %x, <256 x i64> %y) {
589; CHECK-LABEL: icmp_eq_sv_v256i64:
590; CHECK:       # %bb.0:
591; CHECK-NEXT:    lea %s1, 256
592; CHECK-NEXT:    lvl %s1
593; CHECK-NEXT:    vbrd %v1, %s0
594; CHECK-NEXT:    vcmpu.l %v0, %v1, %v0
595; CHECK-NEXT:    vfmk.l.eq %vm1, %v0
596; CHECK-NEXT:    b.l.t (, %s10)
597  %xins = insertelement <256 x i64> undef, i64 %x, i32 0
598  %vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
599  %z = icmp eq <256 x i64> %vx, %y
600  ret <256 x i1> %z
601}
602
603; Function Attrs: nounwind
604define fastcc <256 x i1> @icmp_eq_vs_v256i64(<256 x i64> %x, i64 %y) {
605; CHECK-LABEL: icmp_eq_vs_v256i64:
606; CHECK:       # %bb.0:
607; CHECK-NEXT:    lea %s1, 256
608; CHECK-NEXT:    lvl %s1
609; CHECK-NEXT:    vbrd %v1, %s0
610; CHECK-NEXT:    vcmpu.l %v0, %v0, %v1
611; CHECK-NEXT:    vfmk.l.eq %vm1, %v0
612; CHECK-NEXT:    b.l.t (, %s10)
613  %yins = insertelement <256 x i64> undef, i64 %y, i32 0
614  %vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer
615  %z = icmp eq <256 x i64> %x, %vy
616  ret <256 x i1> %z
617}
618
619define fastcc <256 x i1> @icmp_ne_vv_v256i64(<256 x i64> %x, <256 x i64> %y) {
620; CHECK-LABEL: icmp_ne_vv_v256i64:
621; CHECK:       # %bb.0:
622; CHECK-NEXT:    lea %s0, 256
623; CHECK-NEXT:    lvl %s0
624; CHECK-NEXT:    vcmpu.l %v0, %v0, %v1
625; CHECK-NEXT:    vfmk.l.ne %vm1, %v0
626; CHECK-NEXT:    b.l.t (, %s10)
627  %z = icmp ne <256 x i64> %x, %y
628  ret <256 x i1> %z
629}
630
631; Function Attrs: nounwind
632define fastcc <256 x i1> @icmp_ne_sv_v256i64(i64 %x, <256 x i64> %y) {
633; CHECK-LABEL: icmp_ne_sv_v256i64:
634; CHECK:       # %bb.0:
635; CHECK-NEXT:    lea %s1, 256
636; CHECK-NEXT:    lvl %s1
637; CHECK-NEXT:    vbrd %v1, %s0
638; CHECK-NEXT:    vcmpu.l %v0, %v1, %v0
639; CHECK-NEXT:    vfmk.l.ne %vm1, %v0
640; CHECK-NEXT:    b.l.t (, %s10)
641  %xins = insertelement <256 x i64> undef, i64 %x, i32 0
642  %vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
643  %z = icmp ne <256 x i64> %vx, %y
644  ret <256 x i1> %z
645}
646
647; Function Attrs: nounwind
648define fastcc <256 x i1> @icmp_ne_vs_v256i64(<256 x i64> %x, i64 %y) {
649; CHECK-LABEL: icmp_ne_vs_v256i64:
650; CHECK:       # %bb.0:
651; CHECK-NEXT:    lea %s1, 256
652; CHECK-NEXT:    lvl %s1
653; CHECK-NEXT:    vbrd %v1, %s0
654; CHECK-NEXT:    vcmpu.l %v0, %v0, %v1
655; CHECK-NEXT:    vfmk.l.ne %vm1, %v0
656; CHECK-NEXT:    b.l.t (, %s10)
657  %yins = insertelement <256 x i64> undef, i64 %y, i32 0
658  %vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer
659  %z = icmp ne <256 x i64> %x, %vy
660  ret <256 x i1> %z
661}
662
663; Function Attrs: nounwind
664define fastcc <256 x i1> @icmp_sle_vv_v256i64(<256 x i64> %x, <256 x i64> %y) {
665; CHECK-LABEL: icmp_sle_vv_v256i64:
666; CHECK:       # %bb.0:
667; CHECK-NEXT:    lea %s0, 256
668; CHECK-NEXT:    lvl %s0
669; CHECK-NEXT:    vcmps.l %v0, %v0, %v1
670; CHECK-NEXT:    vfmk.l.le %vm1, %v0
671; CHECK-NEXT:    b.l.t (, %s10)
672  %z = icmp sle <256 x i64> %x, %y
673  ret <256 x i1> %z
674}
675
676; Function Attrs: nounwind
677define fastcc <256 x i1> @icmp_sle_sv_v256i64(i64 %x, <256 x i64> %y) {
678; CHECK-LABEL: icmp_sle_sv_v256i64:
679; CHECK:       # %bb.0:
680; CHECK-NEXT:    lea %s1, 256
681; CHECK-NEXT:    lvl %s1
682; CHECK-NEXT:    vbrd %v1, %s0
683; CHECK-NEXT:    vcmps.l %v0, %v1, %v0
684; CHECK-NEXT:    vfmk.l.le %vm1, %v0
685; CHECK-NEXT:    b.l.t (, %s10)
686  %xins = insertelement <256 x i64> undef, i64 %x, i32 0
687  %vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
688  %z = icmp sle <256 x i64> %vx, %y
689  ret <256 x i1> %z
690}
691
692; Function Attrs: nounwind
693define fastcc <256 x i1> @icmp_sle_vs_v256i64(<256 x i64> %x, i64 %y) {
694; CHECK-LABEL: icmp_sle_vs_v256i64:
695; CHECK:       # %bb.0:
696; CHECK-NEXT:    lea %s1, 256
697; CHECK-NEXT:    lvl %s1
698; CHECK-NEXT:    vbrd %v1, %s0
699; CHECK-NEXT:    vcmps.l %v0, %v0, %v1
700; CHECK-NEXT:    vfmk.l.le %vm1, %v0
701; CHECK-NEXT:    b.l.t (, %s10)
702  %yins = insertelement <256 x i64> undef, i64 %y, i32 0
703  %vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer
704  %z = icmp sle <256 x i64> %x, %vy
705  ret <256 x i1> %z
706}
707
708; Function Attrs: nounwind
709define fastcc <256 x i1> @icmp_slt_vv_v256i64(<256 x i64> %x, <256 x i64> %y) {
710; CHECK-LABEL: icmp_slt_vv_v256i64:
711; CHECK:       # %bb.0:
712; CHECK-NEXT:    lea %s0, 256
713; CHECK-NEXT:    lvl %s0
714; CHECK-NEXT:    vcmps.l %v0, %v0, %v1
715; CHECK-NEXT:    vfmk.l.lt %vm1, %v0
716; CHECK-NEXT:    b.l.t (, %s10)
717  %z = icmp slt <256 x i64> %x, %y
718  ret <256 x i1> %z
719}
720
721; Function Attrs: nounwind
722define fastcc <256 x i1> @icmp_slt_sv_v256i64(i64 %x, <256 x i64> %y) {
723; CHECK-LABEL: icmp_slt_sv_v256i64:
724; CHECK:       # %bb.0:
725; CHECK-NEXT:    lea %s1, 256
726; CHECK-NEXT:    lvl %s1
727; CHECK-NEXT:    vbrd %v1, %s0
728; CHECK-NEXT:    vcmps.l %v0, %v1, %v0
729; CHECK-NEXT:    vfmk.l.lt %vm1, %v0
730; CHECK-NEXT:    b.l.t (, %s10)
731  %xins = insertelement <256 x i64> undef, i64 %x, i32 0
732  %vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
733  %z = icmp slt <256 x i64> %vx, %y
734  ret <256 x i1> %z
735}
736
737; Function Attrs: nounwind
738define fastcc <256 x i1> @icmp_slt_vs_v256i64(<256 x i64> %x, i64 %y) {
739; CHECK-LABEL: icmp_slt_vs_v256i64:
740; CHECK:       # %bb.0:
741; CHECK-NEXT:    lea %s1, 256
742; CHECK-NEXT:    lvl %s1
743; CHECK-NEXT:    vbrd %v1, %s0
744; CHECK-NEXT:    vcmps.l %v0, %v0, %v1
745; CHECK-NEXT:    vfmk.l.lt %vm1, %v0
746; CHECK-NEXT:    b.l.t (, %s10)
747  %yins = insertelement <256 x i64> undef, i64 %y, i32 0
748  %vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer
749  %z = icmp slt <256 x i64> %x, %vy
750  ret <256 x i1> %z
751}
752
753
754
755
756; Function Attrs: nounwind
757define fastcc <256 x i1> @icmp_ugt_vv_v256i64(<256 x i64> %x, <256 x i64> %y) {
758; CHECK-LABEL: icmp_ugt_vv_v256i64:
759; CHECK:       # %bb.0:
760; CHECK-NEXT:    lea %s0, 256
761; CHECK-NEXT:    lvl %s0
762; CHECK-NEXT:    vcmpu.l %v0, %v0, %v1
763; CHECK-NEXT:    vfmk.l.gt %vm1, %v0
764; CHECK-NEXT:    b.l.t (, %s10)
765  %z = icmp ugt <256 x i64> %x, %y
766  ret <256 x i1> %z
767}
768
769; Function Attrs: nounwind
770define fastcc <256 x i1> @icmp_ugt_sv_v256i64(i64 %x, <256 x i64> %y) {
771; CHECK-LABEL: icmp_ugt_sv_v256i64:
772; CHECK:       # %bb.0:
773; CHECK-NEXT:    lea %s1, 256
774; CHECK-NEXT:    lvl %s1
775; CHECK-NEXT:    vbrd %v1, %s0
776; CHECK-NEXT:    vcmpu.l %v0, %v1, %v0
777; CHECK-NEXT:    vfmk.l.gt %vm1, %v0
778; CHECK-NEXT:    b.l.t (, %s10)
779  %xins = insertelement <256 x i64> undef, i64 %x, i32 0
780  %vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
781  %z = icmp ugt <256 x i64> %vx, %y
782  ret <256 x i1> %z
783}
784
785; Function Attrs: nounwind
786define fastcc <256 x i1> @icmp_ugt_vs_v256i64(<256 x i64> %x, i64 %y) {
787; CHECK-LABEL: icmp_ugt_vs_v256i64:
788; CHECK:       # %bb.0:
789; CHECK-NEXT:    lea %s1, 256
790; CHECK-NEXT:    lvl %s1
791; CHECK-NEXT:    vbrd %v1, %s0
792; CHECK-NEXT:    vcmpu.l %v0, %v0, %v1
793; CHECK-NEXT:    vfmk.l.gt %vm1, %v0
794; CHECK-NEXT:    b.l.t (, %s10)
795  %yins = insertelement <256 x i64> undef, i64 %y, i32 0
796  %vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer
797  %z = icmp ugt <256 x i64> %x, %vy
798  ret <256 x i1> %z
799}
800
801; Function Attrs: nounwind
802define fastcc <256 x i1> @icmp_uge_vv_v256i64(<256 x i64> %x, <256 x i64> %y) {
803; CHECK-LABEL: icmp_uge_vv_v256i64:
804; CHECK:       # %bb.0:
805; CHECK-NEXT:    lea %s0, 256
806; CHECK-NEXT:    lvl %s0
807; CHECK-NEXT:    vcmpu.l %v0, %v0, %v1
808; CHECK-NEXT:    vfmk.l.ge %vm1, %v0
809; CHECK-NEXT:    b.l.t (, %s10)
810  %z = icmp uge <256 x i64> %x, %y
811  ret <256 x i1> %z
812}
813
814; Function Attrs: nounwind
815define fastcc <256 x i1> @icmp_uge_sv_v256i64(i64 %x, <256 x i64> %y) {
816; CHECK-LABEL: icmp_uge_sv_v256i64:
817; CHECK:       # %bb.0:
818; CHECK-NEXT:    lea %s1, 256
819; CHECK-NEXT:    lvl %s1
820; CHECK-NEXT:    vbrd %v1, %s0
821; CHECK-NEXT:    vcmpu.l %v0, %v1, %v0
822; CHECK-NEXT:    vfmk.l.ge %vm1, %v0
823; CHECK-NEXT:    b.l.t (, %s10)
824  %xins = insertelement <256 x i64> undef, i64 %x, i32 0
825  %vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
826  %z = icmp uge <256 x i64> %vx, %y
827  ret <256 x i1> %z
828}
829
830; Function Attrs: nounwind
831define fastcc <256 x i1> @icmp_uge_vs_v256i64(<256 x i64> %x, i64 %y) {
832; CHECK-LABEL: icmp_uge_vs_v256i64:
833; CHECK:       # %bb.0:
834; CHECK-NEXT:    lea %s1, 256
835; CHECK-NEXT:    lvl %s1
836; CHECK-NEXT:    vbrd %v1, %s0
837; CHECK-NEXT:    vcmpu.l %v0, %v0, %v1
838; CHECK-NEXT:    vfmk.l.ge %vm1, %v0
839; CHECK-NEXT:    b.l.t (, %s10)
840  %yins = insertelement <256 x i64> undef, i64 %y, i32 0
841  %vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer
842  %z = icmp uge <256 x i64> %x, %vy
843  ret <256 x i1> %z
844}
845
846; Function Attrs: nounwind
847define fastcc <256 x i1> @icmp_ule_vv_v256i64(<256 x i64> %x, <256 x i64> %y) {
848; CHECK-LABEL: icmp_ule_vv_v256i64:
849; CHECK:       # %bb.0:
850; CHECK-NEXT:    lea %s0, 256
851; CHECK-NEXT:    lvl %s0
852; CHECK-NEXT:    vcmpu.l %v0, %v0, %v1
853; CHECK-NEXT:    vfmk.l.le %vm1, %v0
854; CHECK-NEXT:    b.l.t (, %s10)
855  %z = icmp ule <256 x i64> %x, %y
856  ret <256 x i1> %z
857}
858
859; Function Attrs: nounwind
860define fastcc <256 x i1> @icmp_ule_sv_v256i64(i64 %x, <256 x i64> %y) {
861; CHECK-LABEL: icmp_ule_sv_v256i64:
862; CHECK:       # %bb.0:
863; CHECK-NEXT:    lea %s1, 256
864; CHECK-NEXT:    lvl %s1
865; CHECK-NEXT:    vbrd %v1, %s0
866; CHECK-NEXT:    vcmpu.l %v0, %v1, %v0
867; CHECK-NEXT:    vfmk.l.le %vm1, %v0
868; CHECK-NEXT:    b.l.t (, %s10)
869  %xins = insertelement <256 x i64> undef, i64 %x, i32 0
870  %vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
871  %z = icmp ule <256 x i64> %vx, %y
872  ret <256 x i1> %z
873}
874
875; Function Attrs: nounwind
876define fastcc <256 x i1> @icmp_ule_vs_v256i64(<256 x i64> %x, i64 %y) {
877; CHECK-LABEL: icmp_ule_vs_v256i64:
878; CHECK:       # %bb.0:
879; CHECK-NEXT:    lea %s1, 256
880; CHECK-NEXT:    lvl %s1
881; CHECK-NEXT:    vbrd %v1, %s0
882; CHECK-NEXT:    vcmpu.l %v0, %v0, %v1
883; CHECK-NEXT:    vfmk.l.le %vm1, %v0
884; CHECK-NEXT:    b.l.t (, %s10)
885  %yins = insertelement <256 x i64> undef, i64 %y, i32 0
886  %vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer
887  %z = icmp ule <256 x i64> %x, %vy
888  ret <256 x i1> %z
889}
890
891; Function Attrs: nounwind
892define fastcc <256 x i1> @icmp_ult_vv_v256i64(<256 x i64> %x, <256 x i64> %y) {
893; CHECK-LABEL: icmp_ult_vv_v256i64:
894; CHECK:       # %bb.0:
895; CHECK-NEXT:    lea %s0, 256
896; CHECK-NEXT:    lvl %s0
897; CHECK-NEXT:    vcmpu.l %v0, %v0, %v1
898; CHECK-NEXT:    vfmk.l.lt %vm1, %v0
899; CHECK-NEXT:    b.l.t (, %s10)
900  %z = icmp ult <256 x i64> %x, %y
901  ret <256 x i1> %z
902}
903
904; Function Attrs: nounwind
905define fastcc <256 x i1> @icmp_ult_sv_v256i64(i64 %x, <256 x i64> %y) {
906; CHECK-LABEL: icmp_ult_sv_v256i64:
907; CHECK:       # %bb.0:
908; CHECK-NEXT:    lea %s1, 256
909; CHECK-NEXT:    lvl %s1
910; CHECK-NEXT:    vbrd %v1, %s0
911; CHECK-NEXT:    vcmpu.l %v0, %v1, %v0
912; CHECK-NEXT:    vfmk.l.lt %vm1, %v0
913; CHECK-NEXT:    b.l.t (, %s10)
914  %xins = insertelement <256 x i64> undef, i64 %x, i32 0
915  %vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
916  %z = icmp ult <256 x i64> %vx, %y
917  ret <256 x i1> %z
918}
919
920; Function Attrs: nounwind
921define fastcc <256 x i1> @icmp_ult_vs_v256i64(<256 x i64> %x, i64 %y) {
922; CHECK-LABEL: icmp_ult_vs_v256i64:
923; CHECK:       # %bb.0:
924; CHECK-NEXT:    lea %s1, 256
925; CHECK-NEXT:    lvl %s1
926; CHECK-NEXT:    vbrd %v1, %s0
927; CHECK-NEXT:    vcmpu.l %v0, %v0, %v1
928; CHECK-NEXT:    vfmk.l.lt %vm1, %v0
929; CHECK-NEXT:    b.l.t (, %s10)
930  %yins = insertelement <256 x i64> undef, i64 %y, i32 0
931  %vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer
932  %z = icmp ult <256 x i64> %x, %vy
933  ret <256 x i1> %z
934}
935