xref: /llvm-project/llvm/test/CodeGen/VE/Vector/vec_fma.ll (revision 5240e0b891fc4bf69d362199f70c94c28a7b9465) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
3
4declare <256 x float> @llvm.fma.v256f32(<256 x float>, <256 x float>, <256 x float>)
5
6define fastcc <256 x float> @test_vec_fma_v256f32_vvv(<256 x float> %i0, <256 x float> %i1, <256 x float> %i2) {
7; CHECK-LABEL: test_vec_fma_v256f32_vvv:
8; CHECK:       # %bb.0:
9; CHECK-NEXT:    lea %s0, 256
10; CHECK-NEXT:    lvl %s0
11; CHECK-NEXT:    vfmad.s %v0, %v2, %v0, %v1
12; CHECK-NEXT:    b.l.t (, %s10)
13  %r0 = call <256 x float> @llvm.fma.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x float> %i2)
14  ret <256 x float> %r0
15}
16
17define fastcc <256 x float> @test_vec_fma_v256f32_rvv(float %s0, <256 x float> %i1, <256 x float> %i2) {
18; CHECK-LABEL: test_vec_fma_v256f32_rvv:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    lea %s1, 256
21; CHECK-NEXT:    lvl %s1
22; CHECK-NEXT:    vfmad.s %v0, %v1, %s0, %v0
23; CHECK-NEXT:    b.l.t (, %s10)
24  %xins = insertelement <256 x float> undef, float %s0, i32 0
25  %i0 = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
26  %r0 = call <256 x float> @llvm.fma.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x float> %i2)
27  ret <256 x float> %r0
28}
29
30define fastcc <256 x float> @test_vec_fma_v256f32_vrv(<256 x float> %i0, float %s1, <256 x float> %i2) {
31; CHECK-LABEL: test_vec_fma_v256f32_vrv:
32; CHECK:       # %bb.0:
33; CHECK-NEXT:    lea %s1, 256
34; CHECK-NEXT:    lvl %s1
35; CHECK-NEXT:    vfmad.s %v0, %v1, %s0, %v0
36; CHECK-NEXT:    b.l.t (, %s10)
37  %yins = insertelement <256 x float> undef, float %s1, i32 0
38  %i1 = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
39  %r0 = call <256 x float> @llvm.fma.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x float> %i2)
40  ret <256 x float> %r0
41}
42
43define fastcc <256 x float> @test_vec_fma_v256f32_vvr(<256 x float> %i0, <256 x float> %i1, float %s2) {
44; CHECK-LABEL: test_vec_fma_v256f32_vvr:
45; CHECK:       # %bb.0:
46; CHECK-NEXT:    lea %s1, 256
47; CHECK-NEXT:    lvl %s1
48; CHECK-NEXT:    vfmad.s %v0, %s0, %v0, %v1
49; CHECK-NEXT:    b.l.t (, %s10)
50  %zins = insertelement <256 x float> undef, float %s2, i32 0
51  %i2 = shufflevector <256 x float> %zins, <256 x float> undef, <256 x i32> zeroinitializer
52  %r0 = call <256 x float> @llvm.fma.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x float> %i2)
53  ret <256 x float> %r0
54}
55
56declare <256 x double> @llvm.fma.v256f64(<256 x double>, <256 x double>, <256 x double>)
57
58define fastcc <256 x double> @test_vec_fma_v256f64_vvv(<256 x double> %i0, <256 x double> %i1, <256 x double> %i2) {
59; CHECK-LABEL: test_vec_fma_v256f64_vvv:
60; CHECK:       # %bb.0:
61; CHECK-NEXT:    lea %s0, 256
62; CHECK-NEXT:    lvl %s0
63; CHECK-NEXT:    vfmad.d %v0, %v2, %v0, %v1
64; CHECK-NEXT:    b.l.t (, %s10)
65  %r0 = call <256 x double> @llvm.fma.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x double> %i2)
66  ret <256 x double> %r0
67}
68
69define fastcc <256 x double> @test_vec_fma_v256f64_rvv(double %s0, <256 x double> %i1, <256 x double> %i2) {
70; CHECK-LABEL: test_vec_fma_v256f64_rvv:
71; CHECK:       # %bb.0:
72; CHECK-NEXT:    lea %s1, 256
73; CHECK-NEXT:    lvl %s1
74; CHECK-NEXT:    vfmad.d %v0, %v1, %s0, %v0
75; CHECK-NEXT:    b.l.t (, %s10)
76  %xins = insertelement <256 x double> undef, double %s0, i32 0
77  %i0 = shufflevector <256 x double> %xins, <256 x double> undef, <256 x i32> zeroinitializer
78  %r0 = call <256 x double> @llvm.fma.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x double> %i2)
79  ret <256 x double> %r0
80}
81
82define fastcc <256 x double> @test_vec_fma_v256f64_vrv(<256 x double> %i0, double %s1, <256 x double> %i2) {
83; CHECK-LABEL: test_vec_fma_v256f64_vrv:
84; CHECK:       # %bb.0:
85; CHECK-NEXT:    lea %s1, 256
86; CHECK-NEXT:    lvl %s1
87; CHECK-NEXT:    vfmad.d %v0, %v1, %s0, %v0
88; CHECK-NEXT:    b.l.t (, %s10)
89  %yins = insertelement <256 x double> undef, double %s1, i32 0
90  %i1 = shufflevector <256 x double> %yins, <256 x double> undef, <256 x i32> zeroinitializer
91  %r0 = call <256 x double> @llvm.fma.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x double> %i2)
92  ret <256 x double> %r0
93}
94
95define fastcc <256 x double> @test_vec_fma_v256f64_vvr(<256 x double> %i0, <256 x double> %i1, double %s2) {
96; CHECK-LABEL: test_vec_fma_v256f64_vvr:
97; CHECK:       # %bb.0:
98; CHECK-NEXT:    lea %s1, 256
99; CHECK-NEXT:    lvl %s1
100; CHECK-NEXT:    vfmad.d %v0, %s0, %v0, %v1
101; CHECK-NEXT:    b.l.t (, %s10)
102  %zins = insertelement <256 x double> undef, double %s2, i32 0
103  %i2 = shufflevector <256 x double> %zins, <256 x double> undef, <256 x i32> zeroinitializer
104  %r0 = call <256 x double> @llvm.fma.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x double> %i2)
105  ret <256 x double> %r0
106}
107