1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s 3 4; <256 x i32> 5 6; Function Attrs: nounwind 7define fastcc <256 x i32> @and_vv_v256i32(<256 x i32> %x, <256 x i32> %y) { 8; CHECK-LABEL: and_vv_v256i32: 9; CHECK: # %bb.0: 10; CHECK-NEXT: lea %s0, 256 11; CHECK-NEXT: lvl %s0 12; CHECK-NEXT: pvand.lo %v0, %v0, %v1 13; CHECK-NEXT: b.l.t (, %s10) 14 %z = and <256 x i32> %x, %y 15 ret <256 x i32> %z 16} 17 18; Function Attrs: nounwind 19define fastcc <256 x i32> @and_sv_v256i32(i32 %x, <256 x i32> %y) { 20; CHECK-LABEL: and_sv_v256i32: 21; CHECK: # %bb.0: 22; CHECK-NEXT: and %s0, %s0, (32)0 23; CHECK-NEXT: lea %s1, 256 24; CHECK-NEXT: lvl %s1 25; CHECK-NEXT: pvand.lo %v0, %s0, %v0 26; CHECK-NEXT: b.l.t (, %s10) 27 %xins = insertelement <256 x i32> undef, i32 %x, i32 0 28 %vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer 29 %z = and <256 x i32> %vx, %y 30 ret <256 x i32> %z 31} 32 33; Function Attrs: nounwind 34define fastcc <256 x i32> @and_vs_v256i32(<256 x i32> %x, i32 %y) { 35; CHECK-LABEL: and_vs_v256i32: 36; CHECK: # %bb.0: 37; CHECK-NEXT: and %s0, %s0, (32)0 38; CHECK-NEXT: lea %s1, 256 39; CHECK-NEXT: lvl %s1 40; CHECK-NEXT: pvand.lo %v0, %s0, %v0 41; CHECK-NEXT: b.l.t (, %s10) 42 %yins = insertelement <256 x i32> undef, i32 %y, i32 0 43 %vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer 44 %z = and <256 x i32> %x, %vy 45 ret <256 x i32> %z 46} 47 48 49 50; <256 x i64> 51 52; Function Attrs: nounwind 53define fastcc <256 x i64> @and_vv_v256i64(<256 x i64> %x, <256 x i64> %y) { 54; CHECK-LABEL: and_vv_v256i64: 55; CHECK: # %bb.0: 56; CHECK-NEXT: lea %s0, 256 57; CHECK-NEXT: lvl %s0 58; CHECK-NEXT: vand %v0, %v0, %v1 59; CHECK-NEXT: b.l.t (, %s10) 60 %z = and <256 x i64> %x, %y 61 ret <256 x i64> %z 62} 63 64; Function Attrs: nounwind 65define fastcc <256 x i64> @and_sv_v256i64(i64 %x, <256 x i64> %y) { 66; CHECK-LABEL: and_sv_v256i64: 67; CHECK: # %bb.0: 68; CHECK-NEXT: lea %s1, 256 69; CHECK-NEXT: lvl %s1 70; CHECK-NEXT: vand %v0, %s0, %v0 71; CHECK-NEXT: b.l.t (, %s10) 72 %xins = insertelement <256 x i64> undef, i64 %x, i32 0 73 %vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer 74 %z = and <256 x i64> %vx, %y 75 ret <256 x i64> %z 76} 77 78; Function Attrs: nounwind 79define fastcc <256 x i64> @and_vs_v256i64(<256 x i64> %x, i64 %y) { 80; CHECK-LABEL: and_vs_v256i64: 81; CHECK: # %bb.0: 82; CHECK-NEXT: lea %s1, 256 83; CHECK-NEXT: lvl %s1 84; CHECK-NEXT: vand %v0, %s0, %v0 85; CHECK-NEXT: b.l.t (, %s10) 86 %yins = insertelement <256 x i64> undef, i64 %y, i32 0 87 %vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer 88 %z = and <256 x i64> %x, %vy 89 ret <256 x i64> %z 90} 91 92; <128 x i64> 93; We expect this to be widened. 94 95; Function Attrs: nounwind 96define fastcc <128 x i64> @and_vv_v128i64(<128 x i64> %x, <128 x i64> %y) { 97; CHECK-LABEL: and_vv_v128i64: 98; CHECK: # %bb.0: 99; CHECK-NEXT: lea %s0, 256 100; CHECK-NEXT: lvl %s0 101; CHECK-NEXT: vand %v0, %v0, %v1 102; CHECK-NEXT: b.l.t (, %s10) 103 %z = and <128 x i64> %x, %y 104 ret <128 x i64> %z 105} 106 107; <256 x i16> 108; We expect promotion. 109 110; Function Attrs: nounwind 111define fastcc <256 x i16> @and_vv_v256i16(<256 x i16> %x, <256 x i16> %y) { 112; CHECK-LABEL: and_vv_v256i16: 113; CHECK: # %bb.0: 114; CHECK-NEXT: lea %s0, 256 115; CHECK-NEXT: lvl %s0 116; CHECK-NEXT: pvand.lo %v0, %v0, %v1 117; CHECK-NEXT: b.l.t (, %s10) 118 %z = and <256 x i16> %x, %y 119 ret <256 x i16> %z 120} 121 122; <128 x i16> 123; We expect this to be scalarized (for now). 124 125; Function Attrs: nounwind 126define fastcc <128 x i16> @and_vv_v128i16(<128 x i16> %x, <128 x i16> %y) { 127; CHECK-LABEL: and_vv_v128i16: 128; CHECK-NOT: vand 129 %z = and <128 x i16> %x, %y 130 ret <128 x i16> %z 131} 132 133