xref: /llvm-project/llvm/test/CodeGen/VE/Vector/storevr.ll (revision b006b60dc993b2e0ba3e412c80709477241b6be6)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=ve-unknown-unknown -mattr=+vpu | FileCheck %s
3
4@v256i64 = common dso_local local_unnamed_addr global <256 x i64> zeroinitializer, align 16
5
6; Function Attrs: norecurse nounwind readonly
7define fastcc void @storev256i64(ptr nocapture, <256 x i64>) {
8; CHECK-LABEL: storev256i64:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    lea %s1, 256
11; CHECK-NEXT:    lvl %s1
12; CHECK-NEXT:    vst %v0, 8, %s0
13; CHECK-NEXT:    b.l.t (, %s10)
14  store <256 x i64> %1, ptr %0, align 16
15  ret void
16}
17
18; Function Attrs: norecurse nounwind readonly
19define fastcc void @storev256i64stk(<256 x i64>) {
20; CHECK-LABEL: storev256i64stk:
21; CHECK:       # %bb.0:
22; CHECK-NEXT:    lea %s11, -2048(, %s11)
23; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB1_2
24; CHECK-NEXT:  # %bb.1:
25; CHECK-NEXT:    ld %s61, 24(, %s14)
26; CHECK-NEXT:    or %s62, 0, %s0
27; CHECK-NEXT:    lea %s63, 315
28; CHECK-NEXT:    shm.l %s63, (%s61)
29; CHECK-NEXT:    shm.l %s8, 8(%s61)
30; CHECK-NEXT:    shm.l %s11, 16(%s61)
31; CHECK-NEXT:    monc
32; CHECK-NEXT:    or %s0, 0, %s62
33; CHECK-NEXT:  .LBB1_2:
34; CHECK-NEXT:    lea %s0, 256
35; CHECK-NEXT:    lea %s1, (, %s11)
36; CHECK-NEXT:    lvl %s0
37; CHECK-NEXT:    vst %v0, 8, %s1
38; CHECK-NEXT:    lea %s11, 2048(, %s11)
39; CHECK-NEXT:    b.l.t (, %s10)
40  %addr = alloca <256 x i64>, align 16
41  store <256 x i64> %0, ptr %addr, align 16
42  ret void
43}
44
45; Function Attrs: norecurse nounwind readonly
46define fastcc void @storev256i64com(<256 x i64>) {
47; CHECK-LABEL: storev256i64com:
48; CHECK:       # %bb.0:
49; CHECK-NEXT:    lea %s0, v256i64@lo
50; CHECK-NEXT:    and %s0, %s0, (32)0
51; CHECK-NEXT:    lea.sl %s0, v256i64@hi(, %s0)
52; CHECK-NEXT:    lea %s1, 256
53; CHECK-NEXT:    lvl %s1
54; CHECK-NEXT:    vst %v0, 8, %s0
55; CHECK-NEXT:    b.l.t (, %s10)
56  store <256 x i64> %0, ptr @v256i64, align 16
57  ret void
58}
59