1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=ve-unknown-unknown -mattr=+vpu | FileCheck %s 3 4@v256i1 = common dso_local local_unnamed_addr global <256 x i1> zeroinitializer, align 4 5@v512i1 = common dso_local local_unnamed_addr global <512 x i1> zeroinitializer, align 4 6 7; Function Attrs: norecurse nounwind readonly 8define fastcc void @storev256i1(ptr nocapture %mp, <256 x i1> %m) { 9; CHECK-LABEL: storev256i1: 10; CHECK: # %bb.0: 11; CHECK-NEXT: svm %s1, %vm1, 3 12; CHECK-NEXT: st %s1, 24(, %s0) 13; CHECK-NEXT: svm %s1, %vm1, 2 14; CHECK-NEXT: st %s1, 16(, %s0) 15; CHECK-NEXT: svm %s1, %vm1, 1 16; CHECK-NEXT: st %s1, 8(, %s0) 17; CHECK-NEXT: svm %s1, %vm1, 0 18; CHECK-NEXT: st %s1, (, %s0) 19; CHECK-NEXT: b.l.t (, %s10) 20 store <256 x i1> %m, ptr %mp, align 16 21 ret void 22} 23 24; Function Attrs: norecurse nounwind readonly 25define fastcc void @storev256i1com(<256 x i1> %m) { 26; CHECK-LABEL: storev256i1com: 27; CHECK: # %bb.0: 28; CHECK-NEXT: svm %s0, %vm1, 3 29; CHECK-NEXT: lea %s1, v256i1@lo 30; CHECK-NEXT: and %s1, %s1, (32)0 31; CHECK-NEXT: lea.sl %s1, v256i1@hi(, %s1) 32; CHECK-NEXT: st %s0, 24(, %s1) 33; CHECK-NEXT: svm %s0, %vm1, 2 34; CHECK-NEXT: st %s0, 16(, %s1) 35; CHECK-NEXT: svm %s0, %vm1, 1 36; CHECK-NEXT: st %s0, 8(, %s1) 37; CHECK-NEXT: svm %s0, %vm1, 0 38; CHECK-NEXT: st %s0, (, %s1) 39; CHECK-NEXT: b.l.t (, %s10) 40 store <256 x i1> %m, ptr @v256i1, align 16 41 ret void 42} 43 44; Function Attrs: norecurse nounwind readonly 45define fastcc void @storev512i1(ptr nocapture %mp, <512 x i1> %m) { 46; CHECK-LABEL: storev512i1: 47; CHECK: # %bb.0: 48; CHECK-NEXT: svm %s1, %vm2, 3 49; CHECK-NEXT: st %s1, 56(, %s0) 50; CHECK-NEXT: svm %s1, %vm2, 2 51; CHECK-NEXT: st %s1, 48(, %s0) 52; CHECK-NEXT: svm %s1, %vm2, 1 53; CHECK-NEXT: st %s1, 40(, %s0) 54; CHECK-NEXT: svm %s1, %vm2, 0 55; CHECK-NEXT: st %s1, 32(, %s0) 56; CHECK-NEXT: svm %s1, %vm3, 3 57; CHECK-NEXT: st %s1, 24(, %s0) 58; CHECK-NEXT: svm %s1, %vm3, 2 59; CHECK-NEXT: st %s1, 16(, %s0) 60; CHECK-NEXT: svm %s1, %vm3, 1 61; CHECK-NEXT: st %s1, 8(, %s0) 62; CHECK-NEXT: svm %s1, %vm3, 0 63; CHECK-NEXT: st %s1, (, %s0) 64; CHECK-NEXT: b.l.t (, %s10) 65 store <512 x i1> %m, ptr %mp, align 16 66 ret void 67} 68 69; Function Attrs: norecurse nounwind readonly 70define fastcc void @storev512i1com(<512 x i1> %m) { 71; CHECK-LABEL: storev512i1com: 72; CHECK: # %bb.0: 73; CHECK-NEXT: svm %s0, %vm2, 3 74; CHECK-NEXT: lea %s1, v512i1@lo 75; CHECK-NEXT: and %s1, %s1, (32)0 76; CHECK-NEXT: lea.sl %s1, v512i1@hi(, %s1) 77; CHECK-NEXT: st %s0, 56(, %s1) 78; CHECK-NEXT: svm %s0, %vm2, 2 79; CHECK-NEXT: st %s0, 48(, %s1) 80; CHECK-NEXT: svm %s0, %vm2, 1 81; CHECK-NEXT: st %s0, 40(, %s1) 82; CHECK-NEXT: svm %s0, %vm2, 0 83; CHECK-NEXT: st %s0, 32(, %s1) 84; CHECK-NEXT: svm %s0, %vm3, 3 85; CHECK-NEXT: st %s0, 24(, %s1) 86; CHECK-NEXT: svm %s0, %vm3, 2 87; CHECK-NEXT: st %s0, 16(, %s1) 88; CHECK-NEXT: svm %s0, %vm3, 1 89; CHECK-NEXT: st %s0, 8(, %s1) 90; CHECK-NEXT: svm %s0, %vm3, 0 91; CHECK-NEXT: st %s0, (, %s1) 92; CHECK-NEXT: b.l.t (, %s10) 93 store <512 x i1> %m, ptr @v512i1, align 16 94 ret void 95} 96