xref: /llvm-project/llvm/test/CodeGen/VE/Vector/insert_elt.ll (revision c2e7c9cb33acbd118fe5011a1607d6cf8e21de34) 
1; RUN: llc < %s -mtriple=ve-unknown-unknown -mattr=+vpu | FileCheck %s
2
3
4;;; <256 x i64>
5
6define fastcc <256 x i64> @insert_rr_v256i64(i32 signext %idx, i64 %s) {
7; CHECK-LABEL: insert_rr_v256i64:
8; CHECK:       # %bb.0:
9; CHECK-NEXT:    and %s0, %s0, (32)0
10; CHECK-NEXT:    lsv %v0(%s0), %s1
11; CHECK-NEXT:    b.l.t (, %s10)
12  %ret = insertelement <256 x i64> undef, i64 %s, i32 %idx
13  ret <256 x i64> %ret
14}
15
16define fastcc <256 x i64> @insert_ri7_v256i64(i64 %s) {
17; CHECK-LABEL: insert_ri7_v256i64:
18; CHECK:       # %bb.0:
19; CHECK-NEXT:    lsv %v0(127), %s0
20; CHECK-NEXT:    b.l.t (, %s10)
21  %ret = insertelement <256 x i64> undef, i64 %s, i32 127
22  ret <256 x i64> %ret
23}
24
25define fastcc <256 x i64> @insert_ri8_v256i64(i64 %s) {
26; CHECK-LABEL: insert_ri8_v256i64:
27; CHECK:       # %bb.0:
28; CHECK-NEXT:    lea %s1, 128
29; CHECK-NEXT:    lsv %v0(%s1), %s0
30; CHECK-NEXT:    b.l.t (, %s10)
31  %ret = insertelement <256 x i64> undef, i64 %s, i32 128
32  ret <256 x i64> %ret
33}
34
35define fastcc <512 x i64> @insert_ri_v512i64(i64 %s) {
36; CHECK-LABEL: insert_ri_v512i64:
37; CHECK:       # %bb.0:
38; CHECK-NEXT:    lsv %v1(116), %s0
39; CHECK-NEXT:    b.l.t (, %s10)
40  %ret = insertelement <512 x i64> undef, i64 %s, i32 372
41  ret <512 x i64> %ret
42}
43
44;;; <256 x i32>
45
46define fastcc <256 x i32> @insert_rr_v256i32(i32 signext %idx, i32 signext %s) {
47; CHECK-LABEL: insert_rr_v256i32:
48; CHECK:       # %bb.0:
49; CHECK-NEXT:    and %s1, %s1, (32)0
50; CHECK-NEXT:    and %s0, %s0, (32)0
51; CHECK-NEXT:    lsv %v0(%s0), %s1
52; CHECK-NEXT:    b.l.t (, %s10)
53  %ret = insertelement <256 x i32> undef, i32 %s, i32 %idx
54  ret <256 x i32> %ret
55}
56
57define fastcc <256 x i32> @insert_ri7_v256i32(i32 signext %s) {
58; CHECK-LABEL: insert_ri7_v256i32:
59; CHECK:       # %bb.0:
60; CHECK-NEXT:    and %s0, %s0, (32)0
61; CHECK-NEXT:    lsv %v0(127), %s0
62; CHECK-NEXT:    b.l.t (, %s10)
63  %ret = insertelement <256 x i32> undef, i32 %s, i32 127
64  ret <256 x i32> %ret
65}
66
67define fastcc <256 x i32> @insert_ri8_v256i32(i32 signext %s) {
68; CHECK-LABEL: insert_ri8_v256i32:
69; CHECK:       # %bb.0:
70; CHECK-NEXT:    and %s0, %s0, (32)0
71; CHECK-NEXT:    lea %s1, 128
72; CHECK-NEXT:    lsv %v0(%s1), %s0
73; CHECK-NEXT:    b.l.t (, %s10)
74  %ret = insertelement <256 x i32> undef, i32 %s, i32 128
75  ret <256 x i32> %ret
76}
77
78define fastcc <512 x i32> @insert_ri_v512i32(i32 signext %s) {
79; CHECK-LABEL: insert_ri_v512i32:
80; CHECK:       # %bb.0:
81; CHECK-NEXT:    lea %s1, 186
82; CHECK-NEXT:    lvs %s2, %v0(%s1)
83; CHECK-NEXT:    and %s2, %s2, (32)0
84; CHECK-NEXT:    sll %s0, %s0, 32
85; CHECK-NEXT:    or %s0, %s2, %s0
86; CHECK-NEXT:    lsv %v0(%s1), %s0
87; CHECK-NEXT:    b.l.t (, %s10)
88  %ret = insertelement <512 x i32> undef, i32 %s, i32 372
89  ret <512 x i32> %ret
90}
91
92define fastcc <512 x i32> @insert_rr_v512i32(i32 signext %idx, i32 signext %s) {
93; CHECK-LABEL: insert_rr_v512i32:
94; CHECK:       # %bb.0:
95; CHECK-NEXT:    and %s1, %s1, (32)0
96; CHECK-NEXT:    nnd %s2, %s0, (63)0
97; CHECK-NEXT:    sla.w.sx %s2, %s2, 5
98; CHECK-NEXT:    sll %s1, %s1, %s2
99; CHECK-NEXT:    lea %s3, -2
100; CHECK-NEXT:    and %s3, %s3, (32)0
101; CHECK-NEXT:    and %s0, %s0, %s3
102; CHECK-NEXT:    srl %s0, %s0, 1
103; CHECK-NEXT:    lvs %s3, %v0(%s0)
104; CHECK-NEXT:    srl %s2, (32)1, %s2
105; CHECK-NEXT:    and %s2, %s3, %s2
106; CHECK-NEXT:    or %s1, %s2, %s1
107; CHECK-NEXT:    lsv %v0(%s0), %s1
108; CHECK-NEXT:    b.l.t (, %s10)
109  %ret = insertelement <512 x i32> undef, i32 %s, i32 %idx
110  ret <512 x i32> %ret
111}
112
113;;; <256 x double>
114
115define fastcc <256 x double> @insert_rr_v256f64(i32 signext %idx, double %s) {
116; CHECK-LABEL: insert_rr_v256f64:
117; CHECK:       # %bb.0:
118; CHECK-NEXT:    and %s0, %s0, (32)0
119; CHECK-NEXT:    lsv %v0(%s0), %s1
120; CHECK-NEXT:    b.l.t (, %s10)
121  %ret = insertelement <256 x double> undef, double %s, i32 %idx
122  ret <256 x double> %ret
123}
124
125define fastcc <256 x double> @insert_ri7_v256f64(double %s) {
126; CHECK-LABEL: insert_ri7_v256f64:
127; CHECK:       # %bb.0:
128; CHECK-NEXT:    lsv %v0(127), %s0
129; CHECK-NEXT:    b.l.t (, %s10)
130  %ret = insertelement <256 x double> undef, double %s, i32 127
131  ret <256 x double> %ret
132}
133
134define fastcc <256 x double> @insert_ri8_v256f64(double %s) {
135; CHECK-LABEL: insert_ri8_v256f64:
136; CHECK:       # %bb.0:
137; CHECK-NEXT:    lea %s1, 128
138; CHECK-NEXT:    lsv %v0(%s1), %s0
139; CHECK-NEXT:    b.l.t (, %s10)
140  %ret = insertelement <256 x double> undef, double %s, i32 128
141  ret <256 x double> %ret
142}
143
144define fastcc <512 x double> @insert_ri_v512f64(double %s) {
145; CHECK-LABEL: insert_ri_v512f64:
146; CHECK:       # %bb.0:
147; CHECK-NEXT:    lsv %v1(116), %s0
148; CHECK-NEXT:    b.l.t (, %s10)
149  %ret = insertelement <512 x double> undef, double %s, i32 372
150  ret <512 x double> %ret
151}
152
153;;; <256 x float>
154
155define fastcc <256 x float> @insert_rr_v256f32(i32 signext %idx, float %s) {
156; CHECK-LABEL: insert_rr_v256f32:
157; CHECK:       # %bb.0:
158; CHECK-NEXT:    and %s0, %s0, (32)0
159; CHECK-NEXT:    lsv %v0(%s0), %s1
160; CHECK-NEXT:    b.l.t (, %s10)
161  %ret = insertelement <256 x float> undef, float %s, i32 %idx
162  ret <256 x float> %ret
163}
164
165define fastcc <256 x float> @insert_ri7_v256f32(float %s) {
166; CHECK-LABEL: insert_ri7_v256f32:
167; CHECK:       # %bb.0:
168; CHECK-NEXT:    lsv %v0(127), %s0
169; CHECK-NEXT:    b.l.t (, %s10)
170  %ret = insertelement <256 x float> undef, float %s, i32 127
171  ret <256 x float> %ret
172}
173
174define fastcc <256 x float> @insert_ri8_v256f32(float %s) {
175; CHECK-LABEL: insert_ri8_v256f32:
176; CHECK:       # %bb.0:
177; CHECK-NEXT:    lea %s1, 128
178; CHECK-NEXT:    lsv %v0(%s1), %s0
179; CHECK-NEXT:    b.l.t (, %s10)
180  %ret = insertelement <256 x float> undef, float %s, i32 128
181  ret <256 x float> %ret
182}
183
184define fastcc <512 x float> @insert_ri_v512f32(float %s) {
185; CHECK-LABEL: insert_ri_v512f32:
186; CHECK:       # %bb.0:
187; CHECK-NEXT:    sra.l %s0, %s0, 32
188; CHECK-NEXT:    lea %s1, 186
189; CHECK-NEXT:    lvs %s2, %v0(%s1)
190; CHECK-NEXT:    and %s2, %s2, (32)0
191; CHECK-NEXT:    sll %s0, %s0, 32
192; CHECK-NEXT:    or %s0, %s2, %s0
193; CHECK-NEXT:    lsv %v0(%s1), %s0
194; CHECK-NEXT:    b.l.t (, %s10)
195  %ret = insertelement <512 x float> undef, float %s, i32 372
196  ret <512 x float> %ret
197}
198
199define fastcc <512 x float> @insert_rr_v512f32(i32 signext %idx, float %s) {
200; CHECK-LABEL: insert_rr_v512f32:
201; CHECK:       # %bb.0:
202; CHECK-NEXT:    sra.l %s1, %s1, 32
203; CHECK-NEXT:    lea %s2, -2
204; CHECK-NEXT:    and %s2, %s2, (32)0
205; CHECK-NEXT:    and %s2, %s0, %s2
206; CHECK-NEXT:    srl %s2, %s2, 1
207; CHECK-NEXT:    lvs %s3, %v0(%s2)
208; CHECK-NEXT:    nnd %s0, %s0, (63)0
209; CHECK-NEXT:    sla.w.sx %s0, %s0, 5
210; CHECK-NEXT:    srl %s4, (32)1, %s0
211; CHECK-NEXT:    and %s3, %s3, %s4
212; CHECK-NEXT:    adds.w.zx %s1, %s1, (0)1
213; CHECK-NEXT:    sll %s0, %s1, %s0
214; CHECK-NEXT:    or %s0, %s3, %s0
215; CHECK-NEXT:    lsv %v0(%s2), %s0
216; CHECK-NEXT:    b.l.t (, %s10)
217  %ret = insertelement <512 x float> undef, float %s, i32 %idx
218  ret <512 x float> %ret
219}
220