xref: /llvm-project/llvm/test/CodeGen/VE/VELIntrinsics/vsc.ll (revision 87f308ab3dcf493e19abd41ee06ba9b62d6c851c) 
1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
2
3;;; Test vector scatter intrinsic instructions
4;;;
5;;; Note:
6;;;   We test VSC*vrrvl, VSC*vrzvl, VSC*virvl, VSC*vizvl, VSC*vrrvml,
7;;;   VSC*vrzvml, VSC*virvml, and VSC*vizvml instructions.
8
9; Function Attrs: nounwind writeonly
10define fastcc void @vsc_vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3) {
11; CHECK-LABEL: vsc_vvssl:
12; CHECK:       # %bb.0:
13; CHECK-NEXT:    lea %s2, 256
14; CHECK-NEXT:    lvl %s2
15; CHECK-NEXT:    vsc %v0, %v1, %s0, %s1
16; CHECK-NEXT:    b.l.t (, %s10)
17  tail call void @llvm.ve.vl.vsc.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, i32 256)
18  ret void
19}
20
21; Function Attrs: nounwind writeonly
22declare void @llvm.ve.vl.vsc.vvssl(<256 x double>, <256 x double>, i64, i64, i32)
23
24; Function Attrs: nounwind writeonly
25define fastcc void @vsc_vvssl_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {
26; CHECK-LABEL: vsc_vvssl_imm_1:
27; CHECK:       # %bb.0:
28; CHECK-NEXT:    lea %s1, 256
29; CHECK-NEXT:    lvl %s1
30; CHECK-NEXT:    vsc %v0, %v1, %s0, 0
31; CHECK-NEXT:    b.l.t (, %s10)
32  tail call void @llvm.ve.vl.vsc.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, i32 256)
33  ret void
34}
35
36; Function Attrs: nounwind writeonly
37define fastcc void @vsc_vvssl_imm_2(<256 x double> %0, <256 x double> %1, i64 %2) {
38; CHECK-LABEL: vsc_vvssl_imm_2:
39; CHECK:       # %bb.0:
40; CHECK-NEXT:    lea %s1, 256
41; CHECK-NEXT:    lvl %s1
42; CHECK-NEXT:    vsc %v0, %v1, 8, %s0
43; CHECK-NEXT:    b.l.t (, %s10)
44  tail call void @llvm.ve.vl.vsc.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, i32 256)
45  ret void
46}
47
48; Function Attrs: nounwind writeonly
49define fastcc void @vsc_vvssl_imm_3(<256 x double> %0, <256 x double> %1) {
50; CHECK-LABEL: vsc_vvssl_imm_3:
51; CHECK:       # %bb.0:
52; CHECK-NEXT:    lea %s0, 256
53; CHECK-NEXT:    lvl %s0
54; CHECK-NEXT:    vsc %v0, %v1, 8, 0
55; CHECK-NEXT:    b.l.t (, %s10)
56  tail call void @llvm.ve.vl.vsc.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 0, i32 256)
57  ret void
58}
59
60; Function Attrs: nounwind writeonly
61define fastcc void @vsc_vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4) {
62; CHECK-LABEL: vsc_vvssml:
63; CHECK:       # %bb.0:
64; CHECK-NEXT:    lea %s2, 256
65; CHECK-NEXT:    lvl %s2
66; CHECK-NEXT:    vsc %v0, %v1, %s0, %s1, %vm1
67; CHECK-NEXT:    b.l.t (, %s10)
68  tail call void @llvm.ve.vl.vsc.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4, i32 256)
69  ret void
70}
71
72; Function Attrs: nounwind writeonly
73declare void @llvm.ve.vl.vsc.vvssml(<256 x double>, <256 x double>, i64, i64, <256 x i1>, i32)
74
75; Function Attrs: nounwind writeonly
76define fastcc void @vsc_vvssml_imm_1(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {
77; CHECK-LABEL: vsc_vvssml_imm_1:
78; CHECK:       # %bb.0:
79; CHECK-NEXT:    lea %s1, 256
80; CHECK-NEXT:    lvl %s1
81; CHECK-NEXT:    vsc %v0, %v1, %s0, 0, %vm1
82; CHECK-NEXT:    b.l.t (, %s10)
83  tail call void @llvm.ve.vl.vsc.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, <256 x i1> %3, i32 256)
84  ret void
85}
86
87; Function Attrs: nounwind writeonly
88define fastcc void @vsc_vvssml_imm_2(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {
89; CHECK-LABEL: vsc_vvssml_imm_2:
90; CHECK:       # %bb.0:
91; CHECK-NEXT:    lea %s1, 256
92; CHECK-NEXT:    lvl %s1
93; CHECK-NEXT:    vsc %v0, %v1, 8, %s0, %vm1
94; CHECK-NEXT:    b.l.t (, %s10)
95  tail call void @llvm.ve.vl.vsc.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, <256 x i1> %3, i32 256)
96  ret void
97}
98
99; Function Attrs: nounwind writeonly
100define fastcc void @vsc_vvssml_imm_3(<256 x double> %0, <256 x double> %1, <256 x i1> %2) {
101; CHECK-LABEL: vsc_vvssml_imm_3:
102; CHECK:       # %bb.0:
103; CHECK-NEXT:    lea %s0, 256
104; CHECK-NEXT:    lvl %s0
105; CHECK-NEXT:    vsc %v0, %v1, 8, 0, %vm1
106; CHECK-NEXT:    b.l.t (, %s10)
107  tail call void @llvm.ve.vl.vsc.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 0, <256 x i1> %2, i32 256)
108  ret void
109}
110
111; Function Attrs: nounwind writeonly
112define fastcc void @vsc_vvssl_no_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {
113; CHECK-LABEL: vsc_vvssl_no_imm_1:
114; CHECK:       # %bb.0:
115; CHECK-NEXT:    lea %s1, 256
116; CHECK-NEXT:    or %s2, 8, (0)1
117; CHECK-NEXT:    lvl %s1
118; CHECK-NEXT:    vsc %v0, %v1, %s0, %s2
119; CHECK-NEXT:    b.l.t (, %s10)
120  tail call void @llvm.ve.vl.vsc.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 8, i32 256)
121  ret void
122}
123
124; Function Attrs: nounwind writeonly
125define fastcc void @vscnc_vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3) {
126; CHECK-LABEL: vscnc_vvssl:
127; CHECK:       # %bb.0:
128; CHECK-NEXT:    lea %s2, 256
129; CHECK-NEXT:    lvl %s2
130; CHECK-NEXT:    vsc.nc %v0, %v1, %s0, %s1
131; CHECK-NEXT:    b.l.t (, %s10)
132  tail call void @llvm.ve.vl.vscnc.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, i32 256)
133  ret void
134}
135
136; Function Attrs: nounwind writeonly
137declare void @llvm.ve.vl.vscnc.vvssl(<256 x double>, <256 x double>, i64, i64, i32)
138
139; Function Attrs: nounwind writeonly
140define fastcc void @vscnc_vvssl_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {
141; CHECK-LABEL: vscnc_vvssl_imm_1:
142; CHECK:       # %bb.0:
143; CHECK-NEXT:    lea %s1, 256
144; CHECK-NEXT:    lvl %s1
145; CHECK-NEXT:    vsc.nc %v0, %v1, %s0, 0
146; CHECK-NEXT:    b.l.t (, %s10)
147  tail call void @llvm.ve.vl.vscnc.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, i32 256)
148  ret void
149}
150
151; Function Attrs: nounwind writeonly
152define fastcc void @vscnc_vvssl_imm_2(<256 x double> %0, <256 x double> %1, i64 %2) {
153; CHECK-LABEL: vscnc_vvssl_imm_2:
154; CHECK:       # %bb.0:
155; CHECK-NEXT:    lea %s1, 256
156; CHECK-NEXT:    lvl %s1
157; CHECK-NEXT:    vsc.nc %v0, %v1, 8, %s0
158; CHECK-NEXT:    b.l.t (, %s10)
159  tail call void @llvm.ve.vl.vscnc.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, i32 256)
160  ret void
161}
162
163; Function Attrs: nounwind writeonly
164define fastcc void @vscnc_vvssl_imm_3(<256 x double> %0, <256 x double> %1) {
165; CHECK-LABEL: vscnc_vvssl_imm_3:
166; CHECK:       # %bb.0:
167; CHECK-NEXT:    lea %s0, 256
168; CHECK-NEXT:    lvl %s0
169; CHECK-NEXT:    vsc.nc %v0, %v1, 8, 0
170; CHECK-NEXT:    b.l.t (, %s10)
171  tail call void @llvm.ve.vl.vscnc.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 0, i32 256)
172  ret void
173}
174
175; Function Attrs: nounwind writeonly
176define fastcc void @vscnc_vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4) {
177; CHECK-LABEL: vscnc_vvssml:
178; CHECK:       # %bb.0:
179; CHECK-NEXT:    lea %s2, 256
180; CHECK-NEXT:    lvl %s2
181; CHECK-NEXT:    vsc.nc %v0, %v1, %s0, %s1, %vm1
182; CHECK-NEXT:    b.l.t (, %s10)
183  tail call void @llvm.ve.vl.vscnc.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4, i32 256)
184  ret void
185}
186
187; Function Attrs: nounwind writeonly
188declare void @llvm.ve.vl.vscnc.vvssml(<256 x double>, <256 x double>, i64, i64, <256 x i1>, i32)
189
190; Function Attrs: nounwind writeonly
191define fastcc void @vscnc_vvssml_imm_1(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {
192; CHECK-LABEL: vscnc_vvssml_imm_1:
193; CHECK:       # %bb.0:
194; CHECK-NEXT:    lea %s1, 256
195; CHECK-NEXT:    lvl %s1
196; CHECK-NEXT:    vsc.nc %v0, %v1, %s0, 0, %vm1
197; CHECK-NEXT:    b.l.t (, %s10)
198  tail call void @llvm.ve.vl.vscnc.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, <256 x i1> %3, i32 256)
199  ret void
200}
201
202; Function Attrs: nounwind writeonly
203define fastcc void @vscnc_vvssml_imm_2(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {
204; CHECK-LABEL: vscnc_vvssml_imm_2:
205; CHECK:       # %bb.0:
206; CHECK-NEXT:    lea %s1, 256
207; CHECK-NEXT:    lvl %s1
208; CHECK-NEXT:    vsc.nc %v0, %v1, 8, %s0, %vm1
209; CHECK-NEXT:    b.l.t (, %s10)
210  tail call void @llvm.ve.vl.vscnc.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, <256 x i1> %3, i32 256)
211  ret void
212}
213
214; Function Attrs: nounwind writeonly
215define fastcc void @vscnc_vvssml_imm_3(<256 x double> %0, <256 x double> %1, <256 x i1> %2) {
216; CHECK-LABEL: vscnc_vvssml_imm_3:
217; CHECK:       # %bb.0:
218; CHECK-NEXT:    lea %s0, 256
219; CHECK-NEXT:    lvl %s0
220; CHECK-NEXT:    vsc.nc %v0, %v1, 8, 0, %vm1
221; CHECK-NEXT:    b.l.t (, %s10)
222  tail call void @llvm.ve.vl.vscnc.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 0, <256 x i1> %2, i32 256)
223  ret void
224}
225
226; Function Attrs: nounwind writeonly
227define fastcc void @vscnc_vvssl_no_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {
228; CHECK-LABEL: vscnc_vvssl_no_imm_1:
229; CHECK:       # %bb.0:
230; CHECK-NEXT:    lea %s1, 256
231; CHECK-NEXT:    or %s2, 8, (0)1
232; CHECK-NEXT:    lvl %s1
233; CHECK-NEXT:    vsc.nc %v0, %v1, %s0, %s2
234; CHECK-NEXT:    b.l.t (, %s10)
235  tail call void @llvm.ve.vl.vscnc.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 8, i32 256)
236  ret void
237}
238
239; Function Attrs: nounwind writeonly
240define fastcc void @vscot_vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3) {
241; CHECK-LABEL: vscot_vvssl:
242; CHECK:       # %bb.0:
243; CHECK-NEXT:    lea %s2, 256
244; CHECK-NEXT:    lvl %s2
245; CHECK-NEXT:    vsc.ot %v0, %v1, %s0, %s1
246; CHECK-NEXT:    b.l.t (, %s10)
247  tail call void @llvm.ve.vl.vscot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, i32 256)
248  ret void
249}
250
251; Function Attrs: nounwind writeonly
252declare void @llvm.ve.vl.vscot.vvssl(<256 x double>, <256 x double>, i64, i64, i32)
253
254; Function Attrs: nounwind writeonly
255define fastcc void @vscot_vvssl_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {
256; CHECK-LABEL: vscot_vvssl_imm_1:
257; CHECK:       # %bb.0:
258; CHECK-NEXT:    lea %s1, 256
259; CHECK-NEXT:    lvl %s1
260; CHECK-NEXT:    vsc.ot %v0, %v1, %s0, 0
261; CHECK-NEXT:    b.l.t (, %s10)
262  tail call void @llvm.ve.vl.vscot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, i32 256)
263  ret void
264}
265
266; Function Attrs: nounwind writeonly
267define fastcc void @vscot_vvssl_imm_2(<256 x double> %0, <256 x double> %1, i64 %2) {
268; CHECK-LABEL: vscot_vvssl_imm_2:
269; CHECK:       # %bb.0:
270; CHECK-NEXT:    lea %s1, 256
271; CHECK-NEXT:    lvl %s1
272; CHECK-NEXT:    vsc.ot %v0, %v1, 8, %s0
273; CHECK-NEXT:    b.l.t (, %s10)
274  tail call void @llvm.ve.vl.vscot.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, i32 256)
275  ret void
276}
277
278; Function Attrs: nounwind writeonly
279define fastcc void @vscot_vvssl_imm_3(<256 x double> %0, <256 x double> %1) {
280; CHECK-LABEL: vscot_vvssl_imm_3:
281; CHECK:       # %bb.0:
282; CHECK-NEXT:    lea %s0, 256
283; CHECK-NEXT:    lvl %s0
284; CHECK-NEXT:    vsc.ot %v0, %v1, 8, 0
285; CHECK-NEXT:    b.l.t (, %s10)
286  tail call void @llvm.ve.vl.vscot.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 0, i32 256)
287  ret void
288}
289
290; Function Attrs: nounwind writeonly
291define fastcc void @vscot_vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4) {
292; CHECK-LABEL: vscot_vvssml:
293; CHECK:       # %bb.0:
294; CHECK-NEXT:    lea %s2, 256
295; CHECK-NEXT:    lvl %s2
296; CHECK-NEXT:    vsc.ot %v0, %v1, %s0, %s1, %vm1
297; CHECK-NEXT:    b.l.t (, %s10)
298  tail call void @llvm.ve.vl.vscot.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4, i32 256)
299  ret void
300}
301
302; Function Attrs: nounwind writeonly
303declare void @llvm.ve.vl.vscot.vvssml(<256 x double>, <256 x double>, i64, i64, <256 x i1>, i32)
304
305; Function Attrs: nounwind writeonly
306define fastcc void @vscot_vvssml_imm_1(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {
307; CHECK-LABEL: vscot_vvssml_imm_1:
308; CHECK:       # %bb.0:
309; CHECK-NEXT:    lea %s1, 256
310; CHECK-NEXT:    lvl %s1
311; CHECK-NEXT:    vsc.ot %v0, %v1, %s0, 0, %vm1
312; CHECK-NEXT:    b.l.t (, %s10)
313  tail call void @llvm.ve.vl.vscot.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, <256 x i1> %3, i32 256)
314  ret void
315}
316
317; Function Attrs: nounwind writeonly
318define fastcc void @vscot_vvssml_imm_2(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {
319; CHECK-LABEL: vscot_vvssml_imm_2:
320; CHECK:       # %bb.0:
321; CHECK-NEXT:    lea %s1, 256
322; CHECK-NEXT:    lvl %s1
323; CHECK-NEXT:    vsc.ot %v0, %v1, 8, %s0, %vm1
324; CHECK-NEXT:    b.l.t (, %s10)
325  tail call void @llvm.ve.vl.vscot.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, <256 x i1> %3, i32 256)
326  ret void
327}
328
329; Function Attrs: nounwind writeonly
330define fastcc void @vscot_vvssml_imm_3(<256 x double> %0, <256 x double> %1, <256 x i1> %2) {
331; CHECK-LABEL: vscot_vvssml_imm_3:
332; CHECK:       # %bb.0:
333; CHECK-NEXT:    lea %s0, 256
334; CHECK-NEXT:    lvl %s0
335; CHECK-NEXT:    vsc.ot %v0, %v1, 8, 0, %vm1
336; CHECK-NEXT:    b.l.t (, %s10)
337  tail call void @llvm.ve.vl.vscot.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 0, <256 x i1> %2, i32 256)
338  ret void
339}
340
341; Function Attrs: nounwind writeonly
342define fastcc void @vscot_vvssl_no_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {
343; CHECK-LABEL: vscot_vvssl_no_imm_1:
344; CHECK:       # %bb.0:
345; CHECK-NEXT:    lea %s1, 256
346; CHECK-NEXT:    or %s2, 8, (0)1
347; CHECK-NEXT:    lvl %s1
348; CHECK-NEXT:    vsc.ot %v0, %v1, %s0, %s2
349; CHECK-NEXT:    b.l.t (, %s10)
350  tail call void @llvm.ve.vl.vscot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 8, i32 256)
351  ret void
352}
353
354; Function Attrs: nounwind writeonly
355define fastcc void @vscncot_vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3) {
356; CHECK-LABEL: vscncot_vvssl:
357; CHECK:       # %bb.0:
358; CHECK-NEXT:    lea %s2, 256
359; CHECK-NEXT:    lvl %s2
360; CHECK-NEXT:    vsc.nc.ot %v0, %v1, %s0, %s1
361; CHECK-NEXT:    b.l.t (, %s10)
362  tail call void @llvm.ve.vl.vscncot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, i32 256)
363  ret void
364}
365
366; Function Attrs: nounwind writeonly
367declare void @llvm.ve.vl.vscncot.vvssl(<256 x double>, <256 x double>, i64, i64, i32)
368
369; Function Attrs: nounwind writeonly
370define fastcc void @vscncot_vvssl_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {
371; CHECK-LABEL: vscncot_vvssl_imm_1:
372; CHECK:       # %bb.0:
373; CHECK-NEXT:    lea %s1, 256
374; CHECK-NEXT:    lvl %s1
375; CHECK-NEXT:    vsc.nc.ot %v0, %v1, %s0, 0
376; CHECK-NEXT:    b.l.t (, %s10)
377  tail call void @llvm.ve.vl.vscncot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, i32 256)
378  ret void
379}
380
381; Function Attrs: nounwind writeonly
382define fastcc void @vscncot_vvssl_imm_2(<256 x double> %0, <256 x double> %1, i64 %2) {
383; CHECK-LABEL: vscncot_vvssl_imm_2:
384; CHECK:       # %bb.0:
385; CHECK-NEXT:    lea %s1, 256
386; CHECK-NEXT:    lvl %s1
387; CHECK-NEXT:    vsc.nc.ot %v0, %v1, 8, %s0
388; CHECK-NEXT:    b.l.t (, %s10)
389  tail call void @llvm.ve.vl.vscncot.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, i32 256)
390  ret void
391}
392
393; Function Attrs: nounwind writeonly
394define fastcc void @vscncot_vvssl_imm_3(<256 x double> %0, <256 x double> %1) {
395; CHECK-LABEL: vscncot_vvssl_imm_3:
396; CHECK:       # %bb.0:
397; CHECK-NEXT:    lea %s0, 256
398; CHECK-NEXT:    lvl %s0
399; CHECK-NEXT:    vsc.nc.ot %v0, %v1, 8, 0
400; CHECK-NEXT:    b.l.t (, %s10)
401  tail call void @llvm.ve.vl.vscncot.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 0, i32 256)
402  ret void
403}
404
405; Function Attrs: nounwind writeonly
406define fastcc void @vscncot_vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4) {
407; CHECK-LABEL: vscncot_vvssml:
408; CHECK:       # %bb.0:
409; CHECK-NEXT:    lea %s2, 256
410; CHECK-NEXT:    lvl %s2
411; CHECK-NEXT:    vsc.nc.ot %v0, %v1, %s0, %s1, %vm1
412; CHECK-NEXT:    b.l.t (, %s10)
413  tail call void @llvm.ve.vl.vscncot.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4, i32 256)
414  ret void
415}
416
417; Function Attrs: nounwind writeonly
418declare void @llvm.ve.vl.vscncot.vvssml(<256 x double>, <256 x double>, i64, i64, <256 x i1>, i32)
419
420; Function Attrs: nounwind writeonly
421define fastcc void @vscncot_vvssml_imm_1(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {
422; CHECK-LABEL: vscncot_vvssml_imm_1:
423; CHECK:       # %bb.0:
424; CHECK-NEXT:    lea %s1, 256
425; CHECK-NEXT:    lvl %s1
426; CHECK-NEXT:    vsc.nc.ot %v0, %v1, %s0, 0, %vm1
427; CHECK-NEXT:    b.l.t (, %s10)
428  tail call void @llvm.ve.vl.vscncot.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, <256 x i1> %3, i32 256)
429  ret void
430}
431
432; Function Attrs: nounwind writeonly
433define fastcc void @vscncot_vvssml_imm_2(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {
434; CHECK-LABEL: vscncot_vvssml_imm_2:
435; CHECK:       # %bb.0:
436; CHECK-NEXT:    lea %s1, 256
437; CHECK-NEXT:    lvl %s1
438; CHECK-NEXT:    vsc.nc.ot %v0, %v1, 8, %s0, %vm1
439; CHECK-NEXT:    b.l.t (, %s10)
440  tail call void @llvm.ve.vl.vscncot.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, <256 x i1> %3, i32 256)
441  ret void
442}
443
444; Function Attrs: nounwind writeonly
445define fastcc void @vscncot_vvssml_imm_3(<256 x double> %0, <256 x double> %1, <256 x i1> %2) {
446; CHECK-LABEL: vscncot_vvssml_imm_3:
447; CHECK:       # %bb.0:
448; CHECK-NEXT:    lea %s0, 256
449; CHECK-NEXT:    lvl %s0
450; CHECK-NEXT:    vsc.nc.ot %v0, %v1, 8, 0, %vm1
451; CHECK-NEXT:    b.l.t (, %s10)
452  tail call void @llvm.ve.vl.vscncot.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 0, <256 x i1> %2, i32 256)
453  ret void
454}
455
456; Function Attrs: nounwind writeonly
457define fastcc void @vscncot_vvssl_no_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {
458; CHECK-LABEL: vscncot_vvssl_no_imm_1:
459; CHECK:       # %bb.0:
460; CHECK-NEXT:    lea %s1, 256
461; CHECK-NEXT:    or %s2, 8, (0)1
462; CHECK-NEXT:    lvl %s1
463; CHECK-NEXT:    vsc.nc.ot %v0, %v1, %s0, %s2
464; CHECK-NEXT:    b.l.t (, %s10)
465  tail call void @llvm.ve.vl.vscncot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 8, i32 256)
466  ret void
467}
468
469; Function Attrs: nounwind writeonly
470define fastcc void @vscu_vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3) {
471; CHECK-LABEL: vscu_vvssl:
472; CHECK:       # %bb.0:
473; CHECK-NEXT:    lea %s2, 256
474; CHECK-NEXT:    lvl %s2
475; CHECK-NEXT:    vscu %v0, %v1, %s0, %s1
476; CHECK-NEXT:    b.l.t (, %s10)
477  tail call void @llvm.ve.vl.vscu.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, i32 256)
478  ret void
479}
480
481; Function Attrs: nounwind writeonly
482declare void @llvm.ve.vl.vscu.vvssl(<256 x double>, <256 x double>, i64, i64, i32)
483
484; Function Attrs: nounwind writeonly
485define fastcc void @vscu_vvssl_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {
486; CHECK-LABEL: vscu_vvssl_imm_1:
487; CHECK:       # %bb.0:
488; CHECK-NEXT:    lea %s1, 256
489; CHECK-NEXT:    lvl %s1
490; CHECK-NEXT:    vscu %v0, %v1, %s0, 0
491; CHECK-NEXT:    b.l.t (, %s10)
492  tail call void @llvm.ve.vl.vscu.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, i32 256)
493  ret void
494}
495
496; Function Attrs: nounwind writeonly
497define fastcc void @vscu_vvssl_imm_2(<256 x double> %0, <256 x double> %1, i64 %2) {
498; CHECK-LABEL: vscu_vvssl_imm_2:
499; CHECK:       # %bb.0:
500; CHECK-NEXT:    lea %s1, 256
501; CHECK-NEXT:    lvl %s1
502; CHECK-NEXT:    vscu %v0, %v1, 8, %s0
503; CHECK-NEXT:    b.l.t (, %s10)
504  tail call void @llvm.ve.vl.vscu.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, i32 256)
505  ret void
506}
507
508; Function Attrs: nounwind writeonly
509define fastcc void @vscu_vvssl_imm_3(<256 x double> %0, <256 x double> %1) {
510; CHECK-LABEL: vscu_vvssl_imm_3:
511; CHECK:       # %bb.0:
512; CHECK-NEXT:    lea %s0, 256
513; CHECK-NEXT:    lvl %s0
514; CHECK-NEXT:    vscu %v0, %v1, 8, 0
515; CHECK-NEXT:    b.l.t (, %s10)
516  tail call void @llvm.ve.vl.vscu.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 0, i32 256)
517  ret void
518}
519
520; Function Attrs: nounwind writeonly
521define fastcc void @vscu_vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4) {
522; CHECK-LABEL: vscu_vvssml:
523; CHECK:       # %bb.0:
524; CHECK-NEXT:    lea %s2, 256
525; CHECK-NEXT:    lvl %s2
526; CHECK-NEXT:    vscu %v0, %v1, %s0, %s1, %vm1
527; CHECK-NEXT:    b.l.t (, %s10)
528  tail call void @llvm.ve.vl.vscu.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4, i32 256)
529  ret void
530}
531
532; Function Attrs: nounwind writeonly
533declare void @llvm.ve.vl.vscu.vvssml(<256 x double>, <256 x double>, i64, i64, <256 x i1>, i32)
534
535; Function Attrs: nounwind writeonly
536define fastcc void @vscu_vvssml_imm_1(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {
537; CHECK-LABEL: vscu_vvssml_imm_1:
538; CHECK:       # %bb.0:
539; CHECK-NEXT:    lea %s1, 256
540; CHECK-NEXT:    lvl %s1
541; CHECK-NEXT:    vscu %v0, %v1, %s0, 0, %vm1
542; CHECK-NEXT:    b.l.t (, %s10)
543  tail call void @llvm.ve.vl.vscu.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, <256 x i1> %3, i32 256)
544  ret void
545}
546
547; Function Attrs: nounwind writeonly
548define fastcc void @vscu_vvssml_imm_2(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {
549; CHECK-LABEL: vscu_vvssml_imm_2:
550; CHECK:       # %bb.0:
551; CHECK-NEXT:    lea %s1, 256
552; CHECK-NEXT:    lvl %s1
553; CHECK-NEXT:    vscu %v0, %v1, 8, %s0, %vm1
554; CHECK-NEXT:    b.l.t (, %s10)
555  tail call void @llvm.ve.vl.vscu.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, <256 x i1> %3, i32 256)
556  ret void
557}
558
559; Function Attrs: nounwind writeonly
560define fastcc void @vscu_vvssml_imm_3(<256 x double> %0, <256 x double> %1, <256 x i1> %2) {
561; CHECK-LABEL: vscu_vvssml_imm_3:
562; CHECK:       # %bb.0:
563; CHECK-NEXT:    lea %s0, 256
564; CHECK-NEXT:    lvl %s0
565; CHECK-NEXT:    vscu %v0, %v1, 8, 0, %vm1
566; CHECK-NEXT:    b.l.t (, %s10)
567  tail call void @llvm.ve.vl.vscu.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 0, <256 x i1> %2, i32 256)
568  ret void
569}
570
571; Function Attrs: nounwind writeonly
572define fastcc void @vscu_vvssl_no_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {
573; CHECK-LABEL: vscu_vvssl_no_imm_1:
574; CHECK:       # %bb.0:
575; CHECK-NEXT:    lea %s1, 256
576; CHECK-NEXT:    or %s2, 8, (0)1
577; CHECK-NEXT:    lvl %s1
578; CHECK-NEXT:    vscu %v0, %v1, %s0, %s2
579; CHECK-NEXT:    b.l.t (, %s10)
580  tail call void @llvm.ve.vl.vscu.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 8, i32 256)
581  ret void
582}
583
584; Function Attrs: nounwind writeonly
585define fastcc void @vscunc_vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3) {
586; CHECK-LABEL: vscunc_vvssl:
587; CHECK:       # %bb.0:
588; CHECK-NEXT:    lea %s2, 256
589; CHECK-NEXT:    lvl %s2
590; CHECK-NEXT:    vscu.nc %v0, %v1, %s0, %s1
591; CHECK-NEXT:    b.l.t (, %s10)
592  tail call void @llvm.ve.vl.vscunc.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, i32 256)
593  ret void
594}
595
596; Function Attrs: nounwind writeonly
597declare void @llvm.ve.vl.vscunc.vvssl(<256 x double>, <256 x double>, i64, i64, i32)
598
599; Function Attrs: nounwind writeonly
600define fastcc void @vscunc_vvssl_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {
601; CHECK-LABEL: vscunc_vvssl_imm_1:
602; CHECK:       # %bb.0:
603; CHECK-NEXT:    lea %s1, 256
604; CHECK-NEXT:    lvl %s1
605; CHECK-NEXT:    vscu.nc %v0, %v1, %s0, 0
606; CHECK-NEXT:    b.l.t (, %s10)
607  tail call void @llvm.ve.vl.vscunc.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, i32 256)
608  ret void
609}
610
611; Function Attrs: nounwind writeonly
612define fastcc void @vscunc_vvssl_imm_2(<256 x double> %0, <256 x double> %1, i64 %2) {
613; CHECK-LABEL: vscunc_vvssl_imm_2:
614; CHECK:       # %bb.0:
615; CHECK-NEXT:    lea %s1, 256
616; CHECK-NEXT:    lvl %s1
617; CHECK-NEXT:    vscu.nc %v0, %v1, 8, %s0
618; CHECK-NEXT:    b.l.t (, %s10)
619  tail call void @llvm.ve.vl.vscunc.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, i32 256)
620  ret void
621}
622
623; Function Attrs: nounwind writeonly
624define fastcc void @vscunc_vvssl_imm_3(<256 x double> %0, <256 x double> %1) {
625; CHECK-LABEL: vscunc_vvssl_imm_3:
626; CHECK:       # %bb.0:
627; CHECK-NEXT:    lea %s0, 256
628; CHECK-NEXT:    lvl %s0
629; CHECK-NEXT:    vscu.nc %v0, %v1, 8, 0
630; CHECK-NEXT:    b.l.t (, %s10)
631  tail call void @llvm.ve.vl.vscunc.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 0, i32 256)
632  ret void
633}
634
635; Function Attrs: nounwind writeonly
636define fastcc void @vscunc_vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4) {
637; CHECK-LABEL: vscunc_vvssml:
638; CHECK:       # %bb.0:
639; CHECK-NEXT:    lea %s2, 256
640; CHECK-NEXT:    lvl %s2
641; CHECK-NEXT:    vscu.nc %v0, %v1, %s0, %s1, %vm1
642; CHECK-NEXT:    b.l.t (, %s10)
643  tail call void @llvm.ve.vl.vscunc.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4, i32 256)
644  ret void
645}
646
647; Function Attrs: nounwind writeonly
648declare void @llvm.ve.vl.vscunc.vvssml(<256 x double>, <256 x double>, i64, i64, <256 x i1>, i32)
649
650; Function Attrs: nounwind writeonly
651define fastcc void @vscunc_vvssml_imm_1(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {
652; CHECK-LABEL: vscunc_vvssml_imm_1:
653; CHECK:       # %bb.0:
654; CHECK-NEXT:    lea %s1, 256
655; CHECK-NEXT:    lvl %s1
656; CHECK-NEXT:    vscu.nc %v0, %v1, %s0, 0, %vm1
657; CHECK-NEXT:    b.l.t (, %s10)
658  tail call void @llvm.ve.vl.vscunc.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, <256 x i1> %3, i32 256)
659  ret void
660}
661
662; Function Attrs: nounwind writeonly
663define fastcc void @vscunc_vvssml_imm_2(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {
664; CHECK-LABEL: vscunc_vvssml_imm_2:
665; CHECK:       # %bb.0:
666; CHECK-NEXT:    lea %s1, 256
667; CHECK-NEXT:    lvl %s1
668; CHECK-NEXT:    vscu.nc %v0, %v1, 8, %s0, %vm1
669; CHECK-NEXT:    b.l.t (, %s10)
670  tail call void @llvm.ve.vl.vscunc.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, <256 x i1> %3, i32 256)
671  ret void
672}
673
674; Function Attrs: nounwind writeonly
675define fastcc void @vscunc_vvssml_imm_3(<256 x double> %0, <256 x double> %1, <256 x i1> %2) {
676; CHECK-LABEL: vscunc_vvssml_imm_3:
677; CHECK:       # %bb.0:
678; CHECK-NEXT:    lea %s0, 256
679; CHECK-NEXT:    lvl %s0
680; CHECK-NEXT:    vscu.nc %v0, %v1, 8, 0, %vm1
681; CHECK-NEXT:    b.l.t (, %s10)
682  tail call void @llvm.ve.vl.vscunc.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 0, <256 x i1> %2, i32 256)
683  ret void
684}
685
686; Function Attrs: nounwind writeonly
687define fastcc void @vscunc_vvssl_no_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {
688; CHECK-LABEL: vscunc_vvssl_no_imm_1:
689; CHECK:       # %bb.0:
690; CHECK-NEXT:    lea %s1, 256
691; CHECK-NEXT:    or %s2, 8, (0)1
692; CHECK-NEXT:    lvl %s1
693; CHECK-NEXT:    vscu.nc %v0, %v1, %s0, %s2
694; CHECK-NEXT:    b.l.t (, %s10)
695  tail call void @llvm.ve.vl.vscunc.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 8, i32 256)
696  ret void
697}
698
699; Function Attrs: nounwind writeonly
700define fastcc void @vscuot_vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3) {
701; CHECK-LABEL: vscuot_vvssl:
702; CHECK:       # %bb.0:
703; CHECK-NEXT:    lea %s2, 256
704; CHECK-NEXT:    lvl %s2
705; CHECK-NEXT:    vscu.ot %v0, %v1, %s0, %s1
706; CHECK-NEXT:    b.l.t (, %s10)
707  tail call void @llvm.ve.vl.vscuot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, i32 256)
708  ret void
709}
710
711; Function Attrs: nounwind writeonly
712declare void @llvm.ve.vl.vscuot.vvssl(<256 x double>, <256 x double>, i64, i64, i32)
713
714; Function Attrs: nounwind writeonly
715define fastcc void @vscuot_vvssl_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {
716; CHECK-LABEL: vscuot_vvssl_imm_1:
717; CHECK:       # %bb.0:
718; CHECK-NEXT:    lea %s1, 256
719; CHECK-NEXT:    lvl %s1
720; CHECK-NEXT:    vscu.ot %v0, %v1, %s0, 0
721; CHECK-NEXT:    b.l.t (, %s10)
722  tail call void @llvm.ve.vl.vscuot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, i32 256)
723  ret void
724}
725
726; Function Attrs: nounwind writeonly
727define fastcc void @vscuot_vvssl_imm_2(<256 x double> %0, <256 x double> %1, i64 %2) {
728; CHECK-LABEL: vscuot_vvssl_imm_2:
729; CHECK:       # %bb.0:
730; CHECK-NEXT:    lea %s1, 256
731; CHECK-NEXT:    lvl %s1
732; CHECK-NEXT:    vscu.ot %v0, %v1, 8, %s0
733; CHECK-NEXT:    b.l.t (, %s10)
734  tail call void @llvm.ve.vl.vscuot.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, i32 256)
735  ret void
736}
737
738; Function Attrs: nounwind writeonly
739define fastcc void @vscuot_vvssl_imm_3(<256 x double> %0, <256 x double> %1) {
740; CHECK-LABEL: vscuot_vvssl_imm_3:
741; CHECK:       # %bb.0:
742; CHECK-NEXT:    lea %s0, 256
743; CHECK-NEXT:    lvl %s0
744; CHECK-NEXT:    vscu.ot %v0, %v1, 8, 0
745; CHECK-NEXT:    b.l.t (, %s10)
746  tail call void @llvm.ve.vl.vscuot.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 0, i32 256)
747  ret void
748}
749
750; Function Attrs: nounwind writeonly
751define fastcc void @vscuot_vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4) {
752; CHECK-LABEL: vscuot_vvssml:
753; CHECK:       # %bb.0:
754; CHECK-NEXT:    lea %s2, 256
755; CHECK-NEXT:    lvl %s2
756; CHECK-NEXT:    vscu.ot %v0, %v1, %s0, %s1, %vm1
757; CHECK-NEXT:    b.l.t (, %s10)
758  tail call void @llvm.ve.vl.vscuot.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4, i32 256)
759  ret void
760}
761
762; Function Attrs: nounwind writeonly
763declare void @llvm.ve.vl.vscuot.vvssml(<256 x double>, <256 x double>, i64, i64, <256 x i1>, i32)
764
765; Function Attrs: nounwind writeonly
766define fastcc void @vscuot_vvssml_imm_1(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {
767; CHECK-LABEL: vscuot_vvssml_imm_1:
768; CHECK:       # %bb.0:
769; CHECK-NEXT:    lea %s1, 256
770; CHECK-NEXT:    lvl %s1
771; CHECK-NEXT:    vscu.ot %v0, %v1, %s0, 0, %vm1
772; CHECK-NEXT:    b.l.t (, %s10)
773  tail call void @llvm.ve.vl.vscuot.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, <256 x i1> %3, i32 256)
774  ret void
775}
776
777; Function Attrs: nounwind writeonly
778define fastcc void @vscuot_vvssml_imm_2(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {
779; CHECK-LABEL: vscuot_vvssml_imm_2:
780; CHECK:       # %bb.0:
781; CHECK-NEXT:    lea %s1, 256
782; CHECK-NEXT:    lvl %s1
783; CHECK-NEXT:    vscu.ot %v0, %v1, 8, %s0, %vm1
784; CHECK-NEXT:    b.l.t (, %s10)
785  tail call void @llvm.ve.vl.vscuot.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, <256 x i1> %3, i32 256)
786  ret void
787}
788
789; Function Attrs: nounwind writeonly
790define fastcc void @vscuot_vvssml_imm_3(<256 x double> %0, <256 x double> %1, <256 x i1> %2) {
791; CHECK-LABEL: vscuot_vvssml_imm_3:
792; CHECK:       # %bb.0:
793; CHECK-NEXT:    lea %s0, 256
794; CHECK-NEXT:    lvl %s0
795; CHECK-NEXT:    vscu.ot %v0, %v1, 8, 0, %vm1
796; CHECK-NEXT:    b.l.t (, %s10)
797  tail call void @llvm.ve.vl.vscuot.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 0, <256 x i1> %2, i32 256)
798  ret void
799}
800
801; Function Attrs: nounwind writeonly
802define fastcc void @vscuot_vvssl_no_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {
803; CHECK-LABEL: vscuot_vvssl_no_imm_1:
804; CHECK:       # %bb.0:
805; CHECK-NEXT:    lea %s1, 256
806; CHECK-NEXT:    or %s2, 8, (0)1
807; CHECK-NEXT:    lvl %s1
808; CHECK-NEXT:    vscu.ot %v0, %v1, %s0, %s2
809; CHECK-NEXT:    b.l.t (, %s10)
810  tail call void @llvm.ve.vl.vscuot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 8, i32 256)
811  ret void
812}
813
814; Function Attrs: nounwind writeonly
815define fastcc void @vscuncot_vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3) {
816; CHECK-LABEL: vscuncot_vvssl:
817; CHECK:       # %bb.0:
818; CHECK-NEXT:    lea %s2, 256
819; CHECK-NEXT:    lvl %s2
820; CHECK-NEXT:    vscu.nc.ot %v0, %v1, %s0, %s1
821; CHECK-NEXT:    b.l.t (, %s10)
822  tail call void @llvm.ve.vl.vscuncot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, i32 256)
823  ret void
824}
825
826; Function Attrs: nounwind writeonly
827declare void @llvm.ve.vl.vscuncot.vvssl(<256 x double>, <256 x double>, i64, i64, i32)
828
829; Function Attrs: nounwind writeonly
830define fastcc void @vscuncot_vvssl_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {
831; CHECK-LABEL: vscuncot_vvssl_imm_1:
832; CHECK:       # %bb.0:
833; CHECK-NEXT:    lea %s1, 256
834; CHECK-NEXT:    lvl %s1
835; CHECK-NEXT:    vscu.nc.ot %v0, %v1, %s0, 0
836; CHECK-NEXT:    b.l.t (, %s10)
837  tail call void @llvm.ve.vl.vscuncot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, i32 256)
838  ret void
839}
840
841; Function Attrs: nounwind writeonly
842define fastcc void @vscuncot_vvssl_imm_2(<256 x double> %0, <256 x double> %1, i64 %2) {
843; CHECK-LABEL: vscuncot_vvssl_imm_2:
844; CHECK:       # %bb.0:
845; CHECK-NEXT:    lea %s1, 256
846; CHECK-NEXT:    lvl %s1
847; CHECK-NEXT:    vscu.nc.ot %v0, %v1, 8, %s0
848; CHECK-NEXT:    b.l.t (, %s10)
849  tail call void @llvm.ve.vl.vscuncot.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, i32 256)
850  ret void
851}
852
853; Function Attrs: nounwind writeonly
854define fastcc void @vscuncot_vvssl_imm_3(<256 x double> %0, <256 x double> %1) {
855; CHECK-LABEL: vscuncot_vvssl_imm_3:
856; CHECK:       # %bb.0:
857; CHECK-NEXT:    lea %s0, 256
858; CHECK-NEXT:    lvl %s0
859; CHECK-NEXT:    vscu.nc.ot %v0, %v1, 8, 0
860; CHECK-NEXT:    b.l.t (, %s10)
861  tail call void @llvm.ve.vl.vscuncot.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 0, i32 256)
862  ret void
863}
864
865; Function Attrs: nounwind writeonly
866define fastcc void @vscuncot_vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4) {
867; CHECK-LABEL: vscuncot_vvssml:
868; CHECK:       # %bb.0:
869; CHECK-NEXT:    lea %s2, 256
870; CHECK-NEXT:    lvl %s2
871; CHECK-NEXT:    vscu.nc.ot %v0, %v1, %s0, %s1, %vm1
872; CHECK-NEXT:    b.l.t (, %s10)
873  tail call void @llvm.ve.vl.vscuncot.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4, i32 256)
874  ret void
875}
876
877; Function Attrs: nounwind writeonly
878declare void @llvm.ve.vl.vscuncot.vvssml(<256 x double>, <256 x double>, i64, i64, <256 x i1>, i32)
879
880; Function Attrs: nounwind writeonly
881define fastcc void @vscuncot_vvssml_imm_1(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {
882; CHECK-LABEL: vscuncot_vvssml_imm_1:
883; CHECK:       # %bb.0:
884; CHECK-NEXT:    lea %s1, 256
885; CHECK-NEXT:    lvl %s1
886; CHECK-NEXT:    vscu.nc.ot %v0, %v1, %s0, 0, %vm1
887; CHECK-NEXT:    b.l.t (, %s10)
888  tail call void @llvm.ve.vl.vscuncot.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, <256 x i1> %3, i32 256)
889  ret void
890}
891
892; Function Attrs: nounwind writeonly
893define fastcc void @vscuncot_vvssml_imm_2(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {
894; CHECK-LABEL: vscuncot_vvssml_imm_2:
895; CHECK:       # %bb.0:
896; CHECK-NEXT:    lea %s1, 256
897; CHECK-NEXT:    lvl %s1
898; CHECK-NEXT:    vscu.nc.ot %v0, %v1, 8, %s0, %vm1
899; CHECK-NEXT:    b.l.t (, %s10)
900  tail call void @llvm.ve.vl.vscuncot.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, <256 x i1> %3, i32 256)
901  ret void
902}
903
904; Function Attrs: nounwind writeonly
905define fastcc void @vscuncot_vvssml_imm_3(<256 x double> %0, <256 x double> %1, <256 x i1> %2) {
906; CHECK-LABEL: vscuncot_vvssml_imm_3:
907; CHECK:       # %bb.0:
908; CHECK-NEXT:    lea %s0, 256
909; CHECK-NEXT:    lvl %s0
910; CHECK-NEXT:    vscu.nc.ot %v0, %v1, 8, 0, %vm1
911; CHECK-NEXT:    b.l.t (, %s10)
912  tail call void @llvm.ve.vl.vscuncot.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 0, <256 x i1> %2, i32 256)
913  ret void
914}
915
916; Function Attrs: nounwind writeonly
917define fastcc void @vscuncot_vvssl_no_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {
918; CHECK-LABEL: vscuncot_vvssl_no_imm_1:
919; CHECK:       # %bb.0:
920; CHECK-NEXT:    lea %s1, 256
921; CHECK-NEXT:    or %s2, 8, (0)1
922; CHECK-NEXT:    lvl %s1
923; CHECK-NEXT:    vscu.nc.ot %v0, %v1, %s0, %s2
924; CHECK-NEXT:    b.l.t (, %s10)
925  tail call void @llvm.ve.vl.vscuncot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 8, i32 256)
926  ret void
927}
928
929; Function Attrs: nounwind writeonly
930define fastcc void @vscl_vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3) {
931; CHECK-LABEL: vscl_vvssl:
932; CHECK:       # %bb.0:
933; CHECK-NEXT:    lea %s2, 256
934; CHECK-NEXT:    lvl %s2
935; CHECK-NEXT:    vscl %v0, %v1, %s0, %s1
936; CHECK-NEXT:    b.l.t (, %s10)
937  tail call void @llvm.ve.vl.vscl.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, i32 256)
938  ret void
939}
940
941; Function Attrs: nounwind writeonly
942declare void @llvm.ve.vl.vscl.vvssl(<256 x double>, <256 x double>, i64, i64, i32)
943
944; Function Attrs: nounwind writeonly
945define fastcc void @vscl_vvssl_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {
946; CHECK-LABEL: vscl_vvssl_imm_1:
947; CHECK:       # %bb.0:
948; CHECK-NEXT:    lea %s1, 256
949; CHECK-NEXT:    lvl %s1
950; CHECK-NEXT:    vscl %v0, %v1, %s0, 0
951; CHECK-NEXT:    b.l.t (, %s10)
952  tail call void @llvm.ve.vl.vscl.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, i32 256)
953  ret void
954}
955
956; Function Attrs: nounwind writeonly
957define fastcc void @vscl_vvssl_imm_2(<256 x double> %0, <256 x double> %1, i64 %2) {
958; CHECK-LABEL: vscl_vvssl_imm_2:
959; CHECK:       # %bb.0:
960; CHECK-NEXT:    lea %s1, 256
961; CHECK-NEXT:    lvl %s1
962; CHECK-NEXT:    vscl %v0, %v1, 8, %s0
963; CHECK-NEXT:    b.l.t (, %s10)
964  tail call void @llvm.ve.vl.vscl.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, i32 256)
965  ret void
966}
967
968; Function Attrs: nounwind writeonly
969define fastcc void @vscl_vvssl_imm_3(<256 x double> %0, <256 x double> %1) {
970; CHECK-LABEL: vscl_vvssl_imm_3:
971; CHECK:       # %bb.0:
972; CHECK-NEXT:    lea %s0, 256
973; CHECK-NEXT:    lvl %s0
974; CHECK-NEXT:    vscl %v0, %v1, 8, 0
975; CHECK-NEXT:    b.l.t (, %s10)
976  tail call void @llvm.ve.vl.vscl.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 0, i32 256)
977  ret void
978}
979
980; Function Attrs: nounwind writeonly
981define fastcc void @vscl_vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4) {
982; CHECK-LABEL: vscl_vvssml:
983; CHECK:       # %bb.0:
984; CHECK-NEXT:    lea %s2, 256
985; CHECK-NEXT:    lvl %s2
986; CHECK-NEXT:    vscl %v0, %v1, %s0, %s1, %vm1
987; CHECK-NEXT:    b.l.t (, %s10)
988  tail call void @llvm.ve.vl.vscl.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4, i32 256)
989  ret void
990}
991
992; Function Attrs: nounwind writeonly
993declare void @llvm.ve.vl.vscl.vvssml(<256 x double>, <256 x double>, i64, i64, <256 x i1>, i32)
994
995; Function Attrs: nounwind writeonly
996define fastcc void @vscl_vvssml_imm_1(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {
997; CHECK-LABEL: vscl_vvssml_imm_1:
998; CHECK:       # %bb.0:
999; CHECK-NEXT:    lea %s1, 256
1000; CHECK-NEXT:    lvl %s1
1001; CHECK-NEXT:    vscl %v0, %v1, %s0, 0, %vm1
1002; CHECK-NEXT:    b.l.t (, %s10)
1003  tail call void @llvm.ve.vl.vscl.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, <256 x i1> %3, i32 256)
1004  ret void
1005}
1006
1007; Function Attrs: nounwind writeonly
1008define fastcc void @vscl_vvssml_imm_2(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {
1009; CHECK-LABEL: vscl_vvssml_imm_2:
1010; CHECK:       # %bb.0:
1011; CHECK-NEXT:    lea %s1, 256
1012; CHECK-NEXT:    lvl %s1
1013; CHECK-NEXT:    vscl %v0, %v1, 8, %s0, %vm1
1014; CHECK-NEXT:    b.l.t (, %s10)
1015  tail call void @llvm.ve.vl.vscl.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, <256 x i1> %3, i32 256)
1016  ret void
1017}
1018
1019; Function Attrs: nounwind writeonly
1020define fastcc void @vscl_vvssml_imm_3(<256 x double> %0, <256 x double> %1, <256 x i1> %2) {
1021; CHECK-LABEL: vscl_vvssml_imm_3:
1022; CHECK:       # %bb.0:
1023; CHECK-NEXT:    lea %s0, 256
1024; CHECK-NEXT:    lvl %s0
1025; CHECK-NEXT:    vscl %v0, %v1, 8, 0, %vm1
1026; CHECK-NEXT:    b.l.t (, %s10)
1027  tail call void @llvm.ve.vl.vscl.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 0, <256 x i1> %2, i32 256)
1028  ret void
1029}
1030
1031; Function Attrs: nounwind writeonly
1032define fastcc void @vscl_vvssl_no_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {
1033; CHECK-LABEL: vscl_vvssl_no_imm_1:
1034; CHECK:       # %bb.0:
1035; CHECK-NEXT:    lea %s1, 256
1036; CHECK-NEXT:    or %s2, 8, (0)1
1037; CHECK-NEXT:    lvl %s1
1038; CHECK-NEXT:    vscl %v0, %v1, %s0, %s2
1039; CHECK-NEXT:    b.l.t (, %s10)
1040  tail call void @llvm.ve.vl.vscl.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 8, i32 256)
1041  ret void
1042}
1043
1044; Function Attrs: nounwind writeonly
1045define fastcc void @vsclnc_vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3) {
1046; CHECK-LABEL: vsclnc_vvssl:
1047; CHECK:       # %bb.0:
1048; CHECK-NEXT:    lea %s2, 256
1049; CHECK-NEXT:    lvl %s2
1050; CHECK-NEXT:    vscl.nc %v0, %v1, %s0, %s1
1051; CHECK-NEXT:    b.l.t (, %s10)
1052  tail call void @llvm.ve.vl.vsclnc.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, i32 256)
1053  ret void
1054}
1055
1056; Function Attrs: nounwind writeonly
1057declare void @llvm.ve.vl.vsclnc.vvssl(<256 x double>, <256 x double>, i64, i64, i32)
1058
1059; Function Attrs: nounwind writeonly
1060define fastcc void @vsclnc_vvssl_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {
1061; CHECK-LABEL: vsclnc_vvssl_imm_1:
1062; CHECK:       # %bb.0:
1063; CHECK-NEXT:    lea %s1, 256
1064; CHECK-NEXT:    lvl %s1
1065; CHECK-NEXT:    vscl.nc %v0, %v1, %s0, 0
1066; CHECK-NEXT:    b.l.t (, %s10)
1067  tail call void @llvm.ve.vl.vsclnc.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, i32 256)
1068  ret void
1069}
1070
1071; Function Attrs: nounwind writeonly
1072define fastcc void @vsclnc_vvssl_imm_2(<256 x double> %0, <256 x double> %1, i64 %2) {
1073; CHECK-LABEL: vsclnc_vvssl_imm_2:
1074; CHECK:       # %bb.0:
1075; CHECK-NEXT:    lea %s1, 256
1076; CHECK-NEXT:    lvl %s1
1077; CHECK-NEXT:    vscl.nc %v0, %v1, 8, %s0
1078; CHECK-NEXT:    b.l.t (, %s10)
1079  tail call void @llvm.ve.vl.vsclnc.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, i32 256)
1080  ret void
1081}
1082
1083; Function Attrs: nounwind writeonly
1084define fastcc void @vsclnc_vvssl_imm_3(<256 x double> %0, <256 x double> %1) {
1085; CHECK-LABEL: vsclnc_vvssl_imm_3:
1086; CHECK:       # %bb.0:
1087; CHECK-NEXT:    lea %s0, 256
1088; CHECK-NEXT:    lvl %s0
1089; CHECK-NEXT:    vscl.nc %v0, %v1, 8, 0
1090; CHECK-NEXT:    b.l.t (, %s10)
1091  tail call void @llvm.ve.vl.vsclnc.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 0, i32 256)
1092  ret void
1093}
1094
1095; Function Attrs: nounwind writeonly
1096define fastcc void @vsclnc_vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4) {
1097; CHECK-LABEL: vsclnc_vvssml:
1098; CHECK:       # %bb.0:
1099; CHECK-NEXT:    lea %s2, 256
1100; CHECK-NEXT:    lvl %s2
1101; CHECK-NEXT:    vscl.nc %v0, %v1, %s0, %s1, %vm1
1102; CHECK-NEXT:    b.l.t (, %s10)
1103  tail call void @llvm.ve.vl.vsclnc.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4, i32 256)
1104  ret void
1105}
1106
1107; Function Attrs: nounwind writeonly
1108declare void @llvm.ve.vl.vsclnc.vvssml(<256 x double>, <256 x double>, i64, i64, <256 x i1>, i32)
1109
1110; Function Attrs: nounwind writeonly
1111define fastcc void @vsclnc_vvssml_imm_1(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {
1112; CHECK-LABEL: vsclnc_vvssml_imm_1:
1113; CHECK:       # %bb.0:
1114; CHECK-NEXT:    lea %s1, 256
1115; CHECK-NEXT:    lvl %s1
1116; CHECK-NEXT:    vscl.nc %v0, %v1, %s0, 0, %vm1
1117; CHECK-NEXT:    b.l.t (, %s10)
1118  tail call void @llvm.ve.vl.vsclnc.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, <256 x i1> %3, i32 256)
1119  ret void
1120}
1121
1122; Function Attrs: nounwind writeonly
1123define fastcc void @vsclnc_vvssml_imm_2(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {
1124; CHECK-LABEL: vsclnc_vvssml_imm_2:
1125; CHECK:       # %bb.0:
1126; CHECK-NEXT:    lea %s1, 256
1127; CHECK-NEXT:    lvl %s1
1128; CHECK-NEXT:    vscl.nc %v0, %v1, 8, %s0, %vm1
1129; CHECK-NEXT:    b.l.t (, %s10)
1130  tail call void @llvm.ve.vl.vsclnc.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, <256 x i1> %3, i32 256)
1131  ret void
1132}
1133
1134; Function Attrs: nounwind writeonly
1135define fastcc void @vsclnc_vvssml_imm_3(<256 x double> %0, <256 x double> %1, <256 x i1> %2) {
1136; CHECK-LABEL: vsclnc_vvssml_imm_3:
1137; CHECK:       # %bb.0:
1138; CHECK-NEXT:    lea %s0, 256
1139; CHECK-NEXT:    lvl %s0
1140; CHECK-NEXT:    vscl.nc %v0, %v1, 8, 0, %vm1
1141; CHECK-NEXT:    b.l.t (, %s10)
1142  tail call void @llvm.ve.vl.vsclnc.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 0, <256 x i1> %2, i32 256)
1143  ret void
1144}
1145
1146; Function Attrs: nounwind writeonly
1147define fastcc void @vsclnc_vvssl_no_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {
1148; CHECK-LABEL: vsclnc_vvssl_no_imm_1:
1149; CHECK:       # %bb.0:
1150; CHECK-NEXT:    lea %s1, 256
1151; CHECK-NEXT:    or %s2, 8, (0)1
1152; CHECK-NEXT:    lvl %s1
1153; CHECK-NEXT:    vscl.nc %v0, %v1, %s0, %s2
1154; CHECK-NEXT:    b.l.t (, %s10)
1155  tail call void @llvm.ve.vl.vsclnc.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 8, i32 256)
1156  ret void
1157}
1158
1159; Function Attrs: nounwind writeonly
1160define fastcc void @vsclot_vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3) {
1161; CHECK-LABEL: vsclot_vvssl:
1162; CHECK:       # %bb.0:
1163; CHECK-NEXT:    lea %s2, 256
1164; CHECK-NEXT:    lvl %s2
1165; CHECK-NEXT:    vscl.ot %v0, %v1, %s0, %s1
1166; CHECK-NEXT:    b.l.t (, %s10)
1167  tail call void @llvm.ve.vl.vsclot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, i32 256)
1168  ret void
1169}
1170
1171; Function Attrs: nounwind writeonly
1172declare void @llvm.ve.vl.vsclot.vvssl(<256 x double>, <256 x double>, i64, i64, i32)
1173
1174; Function Attrs: nounwind writeonly
1175define fastcc void @vsclot_vvssl_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {
1176; CHECK-LABEL: vsclot_vvssl_imm_1:
1177; CHECK:       # %bb.0:
1178; CHECK-NEXT:    lea %s1, 256
1179; CHECK-NEXT:    lvl %s1
1180; CHECK-NEXT:    vscl.ot %v0, %v1, %s0, 0
1181; CHECK-NEXT:    b.l.t (, %s10)
1182  tail call void @llvm.ve.vl.vsclot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, i32 256)
1183  ret void
1184}
1185
1186; Function Attrs: nounwind writeonly
1187define fastcc void @vsclot_vvssl_imm_2(<256 x double> %0, <256 x double> %1, i64 %2) {
1188; CHECK-LABEL: vsclot_vvssl_imm_2:
1189; CHECK:       # %bb.0:
1190; CHECK-NEXT:    lea %s1, 256
1191; CHECK-NEXT:    lvl %s1
1192; CHECK-NEXT:    vscl.ot %v0, %v1, 8, %s0
1193; CHECK-NEXT:    b.l.t (, %s10)
1194  tail call void @llvm.ve.vl.vsclot.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, i32 256)
1195  ret void
1196}
1197
1198; Function Attrs: nounwind writeonly
1199define fastcc void @vsclot_vvssl_imm_3(<256 x double> %0, <256 x double> %1) {
1200; CHECK-LABEL: vsclot_vvssl_imm_3:
1201; CHECK:       # %bb.0:
1202; CHECK-NEXT:    lea %s0, 256
1203; CHECK-NEXT:    lvl %s0
1204; CHECK-NEXT:    vscl.ot %v0, %v1, 8, 0
1205; CHECK-NEXT:    b.l.t (, %s10)
1206  tail call void @llvm.ve.vl.vsclot.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 0, i32 256)
1207  ret void
1208}
1209
1210; Function Attrs: nounwind writeonly
1211define fastcc void @vsclot_vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4) {
1212; CHECK-LABEL: vsclot_vvssml:
1213; CHECK:       # %bb.0:
1214; CHECK-NEXT:    lea %s2, 256
1215; CHECK-NEXT:    lvl %s2
1216; CHECK-NEXT:    vscl.ot %v0, %v1, %s0, %s1, %vm1
1217; CHECK-NEXT:    b.l.t (, %s10)
1218  tail call void @llvm.ve.vl.vsclot.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4, i32 256)
1219  ret void
1220}
1221
1222; Function Attrs: nounwind writeonly
1223declare void @llvm.ve.vl.vsclot.vvssml(<256 x double>, <256 x double>, i64, i64, <256 x i1>, i32)
1224
1225; Function Attrs: nounwind writeonly
1226define fastcc void @vsclot_vvssml_imm_1(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {
1227; CHECK-LABEL: vsclot_vvssml_imm_1:
1228; CHECK:       # %bb.0:
1229; CHECK-NEXT:    lea %s1, 256
1230; CHECK-NEXT:    lvl %s1
1231; CHECK-NEXT:    vscl.ot %v0, %v1, %s0, 0, %vm1
1232; CHECK-NEXT:    b.l.t (, %s10)
1233  tail call void @llvm.ve.vl.vsclot.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, <256 x i1> %3, i32 256)
1234  ret void
1235}
1236
1237; Function Attrs: nounwind writeonly
1238define fastcc void @vsclot_vvssml_imm_2(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {
1239; CHECK-LABEL: vsclot_vvssml_imm_2:
1240; CHECK:       # %bb.0:
1241; CHECK-NEXT:    lea %s1, 256
1242; CHECK-NEXT:    lvl %s1
1243; CHECK-NEXT:    vscl.ot %v0, %v1, 8, %s0, %vm1
1244; CHECK-NEXT:    b.l.t (, %s10)
1245  tail call void @llvm.ve.vl.vsclot.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, <256 x i1> %3, i32 256)
1246  ret void
1247}
1248
1249; Function Attrs: nounwind writeonly
1250define fastcc void @vsclot_vvssml_imm_3(<256 x double> %0, <256 x double> %1, <256 x i1> %2) {
1251; CHECK-LABEL: vsclot_vvssml_imm_3:
1252; CHECK:       # %bb.0:
1253; CHECK-NEXT:    lea %s0, 256
1254; CHECK-NEXT:    lvl %s0
1255; CHECK-NEXT:    vscl.ot %v0, %v1, 8, 0, %vm1
1256; CHECK-NEXT:    b.l.t (, %s10)
1257  tail call void @llvm.ve.vl.vsclot.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 0, <256 x i1> %2, i32 256)
1258  ret void
1259}
1260
1261; Function Attrs: nounwind writeonly
1262define fastcc void @vsclot_vvssl_no_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {
1263; CHECK-LABEL: vsclot_vvssl_no_imm_1:
1264; CHECK:       # %bb.0:
1265; CHECK-NEXT:    lea %s1, 256
1266; CHECK-NEXT:    or %s2, 8, (0)1
1267; CHECK-NEXT:    lvl %s1
1268; CHECK-NEXT:    vscl.ot %v0, %v1, %s0, %s2
1269; CHECK-NEXT:    b.l.t (, %s10)
1270  tail call void @llvm.ve.vl.vsclot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 8, i32 256)
1271  ret void
1272}
1273
1274; Function Attrs: nounwind writeonly
1275define fastcc void @vsclncot_vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3) {
1276; CHECK-LABEL: vsclncot_vvssl:
1277; CHECK:       # %bb.0:
1278; CHECK-NEXT:    lea %s2, 256
1279; CHECK-NEXT:    lvl %s2
1280; CHECK-NEXT:    vscl.nc.ot %v0, %v1, %s0, %s1
1281; CHECK-NEXT:    b.l.t (, %s10)
1282  tail call void @llvm.ve.vl.vsclncot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, i32 256)
1283  ret void
1284}
1285
1286; Function Attrs: nounwind writeonly
1287declare void @llvm.ve.vl.vsclncot.vvssl(<256 x double>, <256 x double>, i64, i64, i32)
1288
1289; Function Attrs: nounwind writeonly
1290define fastcc void @vsclncot_vvssl_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {
1291; CHECK-LABEL: vsclncot_vvssl_imm_1:
1292; CHECK:       # %bb.0:
1293; CHECK-NEXT:    lea %s1, 256
1294; CHECK-NEXT:    lvl %s1
1295; CHECK-NEXT:    vscl.nc.ot %v0, %v1, %s0, 0
1296; CHECK-NEXT:    b.l.t (, %s10)
1297  tail call void @llvm.ve.vl.vsclncot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, i32 256)
1298  ret void
1299}
1300
1301; Function Attrs: nounwind writeonly
1302define fastcc void @vsclncot_vvssl_imm_2(<256 x double> %0, <256 x double> %1, i64 %2) {
1303; CHECK-LABEL: vsclncot_vvssl_imm_2:
1304; CHECK:       # %bb.0:
1305; CHECK-NEXT:    lea %s1, 256
1306; CHECK-NEXT:    lvl %s1
1307; CHECK-NEXT:    vscl.nc.ot %v0, %v1, 8, %s0
1308; CHECK-NEXT:    b.l.t (, %s10)
1309  tail call void @llvm.ve.vl.vsclncot.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, i32 256)
1310  ret void
1311}
1312
1313; Function Attrs: nounwind writeonly
1314define fastcc void @vsclncot_vvssl_imm_3(<256 x double> %0, <256 x double> %1) {
1315; CHECK-LABEL: vsclncot_vvssl_imm_3:
1316; CHECK:       # %bb.0:
1317; CHECK-NEXT:    lea %s0, 256
1318; CHECK-NEXT:    lvl %s0
1319; CHECK-NEXT:    vscl.nc.ot %v0, %v1, 8, 0
1320; CHECK-NEXT:    b.l.t (, %s10)
1321  tail call void @llvm.ve.vl.vsclncot.vvssl(<256 x double> %0, <256 x double> %1, i64 8, i64 0, i32 256)
1322  ret void
1323}
1324
1325; Function Attrs: nounwind writeonly
1326define fastcc void @vsclncot_vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4) {
1327; CHECK-LABEL: vsclncot_vvssml:
1328; CHECK:       # %bb.0:
1329; CHECK-NEXT:    lea %s2, 256
1330; CHECK-NEXT:    lvl %s2
1331; CHECK-NEXT:    vscl.nc.ot %v0, %v1, %s0, %s1, %vm1
1332; CHECK-NEXT:    b.l.t (, %s10)
1333  tail call void @llvm.ve.vl.vsclncot.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 %3, <256 x i1> %4, i32 256)
1334  ret void
1335}
1336
1337; Function Attrs: nounwind writeonly
1338declare void @llvm.ve.vl.vsclncot.vvssml(<256 x double>, <256 x double>, i64, i64, <256 x i1>, i32)
1339
1340; Function Attrs: nounwind writeonly
1341define fastcc void @vsclncot_vvssml_imm_1(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {
1342; CHECK-LABEL: vsclncot_vvssml_imm_1:
1343; CHECK:       # %bb.0:
1344; CHECK-NEXT:    lea %s1, 256
1345; CHECK-NEXT:    lvl %s1
1346; CHECK-NEXT:    vscl.nc.ot %v0, %v1, %s0, 0, %vm1
1347; CHECK-NEXT:    b.l.t (, %s10)
1348  tail call void @llvm.ve.vl.vsclncot.vvssml(<256 x double> %0, <256 x double> %1, i64 %2, i64 0, <256 x i1> %3, i32 256)
1349  ret void
1350}
1351
1352; Function Attrs: nounwind writeonly
1353define fastcc void @vsclncot_vvssml_imm_2(<256 x double> %0, <256 x double> %1, i64 %2, <256 x i1> %3) {
1354; CHECK-LABEL: vsclncot_vvssml_imm_2:
1355; CHECK:       # %bb.0:
1356; CHECK-NEXT:    lea %s1, 256
1357; CHECK-NEXT:    lvl %s1
1358; CHECK-NEXT:    vscl.nc.ot %v0, %v1, 8, %s0, %vm1
1359; CHECK-NEXT:    b.l.t (, %s10)
1360  tail call void @llvm.ve.vl.vsclncot.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 %2, <256 x i1> %3, i32 256)
1361  ret void
1362}
1363
1364; Function Attrs: nounwind writeonly
1365define fastcc void @vsclncot_vvssml_imm_3(<256 x double> %0, <256 x double> %1, <256 x i1> %2) {
1366; CHECK-LABEL: vsclncot_vvssml_imm_3:
1367; CHECK:       # %bb.0:
1368; CHECK-NEXT:    lea %s0, 256
1369; CHECK-NEXT:    lvl %s0
1370; CHECK-NEXT:    vscl.nc.ot %v0, %v1, 8, 0, %vm1
1371; CHECK-NEXT:    b.l.t (, %s10)
1372  tail call void @llvm.ve.vl.vsclncot.vvssml(<256 x double> %0, <256 x double> %1, i64 8, i64 0, <256 x i1> %2, i32 256)
1373  ret void
1374}
1375
1376; Function Attrs: nounwind writeonly
1377define fastcc void @vsclncot_vvssl_no_imm_1(<256 x double> %0, <256 x double> %1, i64 %2) {
1378; CHECK-LABEL: vsclncot_vvssl_no_imm_1:
1379; CHECK:       # %bb.0:
1380; CHECK-NEXT:    lea %s1, 256
1381; CHECK-NEXT:    or %s2, 8, (0)1
1382; CHECK-NEXT:    lvl %s1
1383; CHECK-NEXT:    vscl.nc.ot %v0, %v1, %s0, %s2
1384; CHECK-NEXT:    b.l.t (, %s10)
1385  tail call void @llvm.ve.vl.vsclncot.vvssl(<256 x double> %0, <256 x double> %1, i64 %2, i64 8, i32 256)
1386  ret void
1387}
1388