xref: /llvm-project/llvm/test/CodeGen/VE/VELIntrinsics/vgt.ll (revision 87f308ab3dcf493e19abd41ee06ba9b62d6c851c) 
1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
2
3;;; Test vector gather intrinsic instructions
4;;;
5;;; Note:
6;;;   We test VGT*vrrl, VGT*vrrl_v, VGT*vrzl, VGT*vrzl_v, VGT*virl, VGT*virl_v,
7;;;   VGT*vizl, VGT*vizl_v, VGT*vrrml, VGT*vrrml_v, VGT*vrzml, VGT*vrzml_v,
8;;;   VGT*virml, VGT*virml_v, VGT*vizml, and VGT*vizml_v instructions.
9
10; Function Attrs: nounwind readonly
11define fastcc <256 x double> @vgt_vvssl(<256 x double> %0, i64 %1, i64 %2) {
12; CHECK-LABEL: vgt_vvssl:
13; CHECK:       # %bb.0:
14; CHECK-NEXT:    lea %s2, 256
15; CHECK-NEXT:    lvl %s2
16; CHECK-NEXT:    vgt %v0, %v0, %s0, %s1
17; CHECK-NEXT:    b.l.t (, %s10)
18  %4 = tail call fast <256 x double> @llvm.ve.vl.vgt.vvssl(<256 x double> %0, i64 %1, i64 %2, i32 256)
19  ret <256 x double> %4
20}
21
22; Function Attrs: nounwind readonly
23declare <256 x double> @llvm.ve.vl.vgt.vvssl(<256 x double>, i64, i64, i32)
24
25; Function Attrs: nounwind readonly
26define fastcc <256 x double> @vgt_vvssvl(<256 x double> %0, i64 %1, i64 %2, <256 x double> %3) {
27; CHECK-LABEL: vgt_vvssvl:
28; CHECK:       # %bb.0:
29; CHECK-NEXT:    lea %s2, 128
30; CHECK-NEXT:    lvl %s2
31; CHECK-NEXT:    vgt %v1, %v0, %s0, %s1
32; CHECK-NEXT:    lea %s16, 256
33; CHECK-NEXT:    lvl %s16
34; CHECK-NEXT:    vor %v0, (0)1, %v1
35; CHECK-NEXT:    b.l.t (, %s10)
36  %5 = tail call fast <256 x double> @llvm.ve.vl.vgt.vvssvl(<256 x double> %0, i64 %1, i64 %2, <256 x double> %3, i32 128)
37  ret <256 x double> %5
38}
39
40; Function Attrs: nounwind readonly
41declare <256 x double> @llvm.ve.vl.vgt.vvssvl(<256 x double>, i64, i64, <256 x double>, i32)
42
43; Function Attrs: nounwind readonly
44define fastcc <256 x double> @vgt_vvssl_imm_1(<256 x double> %0, i64 %1) {
45; CHECK-LABEL: vgt_vvssl_imm_1:
46; CHECK:       # %bb.0:
47; CHECK-NEXT:    lea %s1, 256
48; CHECK-NEXT:    lvl %s1
49; CHECK-NEXT:    vgt %v0, %v0, %s0, 0
50; CHECK-NEXT:    b.l.t (, %s10)
51  %3 = tail call fast <256 x double> @llvm.ve.vl.vgt.vvssl(<256 x double> %0, i64 %1, i64 0, i32 256)
52  ret <256 x double> %3
53}
54
55; Function Attrs: nounwind readonly
56define fastcc <256 x double> @vgt_vvssvl_imm_1(<256 x double> %0, i64 %1, <256 x double> %2) {
57; CHECK-LABEL: vgt_vvssvl_imm_1:
58; CHECK:       # %bb.0:
59; CHECK-NEXT:    lea %s1, 128
60; CHECK-NEXT:    lvl %s1
61; CHECK-NEXT:    vgt %v1, %v0, %s0, 0
62; CHECK-NEXT:    lea %s16, 256
63; CHECK-NEXT:    lvl %s16
64; CHECK-NEXT:    vor %v0, (0)1, %v1
65; CHECK-NEXT:    b.l.t (, %s10)
66  %4 = tail call fast <256 x double> @llvm.ve.vl.vgt.vvssvl(<256 x double> %0, i64 %1, i64 0, <256 x double> %2, i32 128)
67  ret <256 x double> %4
68}
69
70; Function Attrs: nounwind readonly
71define fastcc <256 x double> @vgt_vvssl_imm_2(<256 x double> %0, i64 %1) {
72; CHECK-LABEL: vgt_vvssl_imm_2:
73; CHECK:       # %bb.0:
74; CHECK-NEXT:    lea %s1, 256
75; CHECK-NEXT:    lvl %s1
76; CHECK-NEXT:    vgt %v0, %v0, 8, %s0
77; CHECK-NEXT:    b.l.t (, %s10)
78  %3 = tail call fast <256 x double> @llvm.ve.vl.vgt.vvssl(<256 x double> %0, i64 8, i64 %1, i32 256)
79  ret <256 x double> %3
80}
81
82; Function Attrs: nounwind readonly
83define fastcc <256 x double> @vgt_vvssvl_imm_2(<256 x double> %0, i64 %1, <256 x double> %2) {
84; CHECK-LABEL: vgt_vvssvl_imm_2:
85; CHECK:       # %bb.0:
86; CHECK-NEXT:    lea %s1, 128
87; CHECK-NEXT:    lvl %s1
88; CHECK-NEXT:    vgt %v1, %v0, 8, %s0
89; CHECK-NEXT:    lea %s16, 256
90; CHECK-NEXT:    lvl %s16
91; CHECK-NEXT:    vor %v0, (0)1, %v1
92; CHECK-NEXT:    b.l.t (, %s10)
93  %4 = tail call fast <256 x double> @llvm.ve.vl.vgt.vvssvl(<256 x double> %0, i64 8, i64 %1, <256 x double> %2, i32 128)
94  ret <256 x double> %4
95}
96
97; Function Attrs: nounwind readonly
98define fastcc <256 x double> @vgt_vvssl_imm_3(<256 x double> %0) {
99; CHECK-LABEL: vgt_vvssl_imm_3:
100; CHECK:       # %bb.0:
101; CHECK-NEXT:    lea %s0, 256
102; CHECK-NEXT:    lvl %s0
103; CHECK-NEXT:    vgt %v0, %v0, 8, 0
104; CHECK-NEXT:    b.l.t (, %s10)
105  %2 = tail call fast <256 x double> @llvm.ve.vl.vgt.vvssl(<256 x double> %0, i64 8, i64 0, i32 256)
106  ret <256 x double> %2
107}
108
109; Function Attrs: nounwind readonly
110define fastcc <256 x double> @vgt_vvssvl_imm_3(<256 x double> %0, <256 x double> %1) {
111; CHECK-LABEL: vgt_vvssvl_imm_3:
112; CHECK:       # %bb.0:
113; CHECK-NEXT:    lea %s0, 128
114; CHECK-NEXT:    lvl %s0
115; CHECK-NEXT:    vgt %v1, %v0, 8, 0
116; CHECK-NEXT:    lea %s16, 256
117; CHECK-NEXT:    lvl %s16
118; CHECK-NEXT:    vor %v0, (0)1, %v1
119; CHECK-NEXT:    b.l.t (, %s10)
120  %3 = tail call fast <256 x double> @llvm.ve.vl.vgt.vvssvl(<256 x double> %0, i64 8, i64 0, <256 x double> %1, i32 128)
121  ret <256 x double> %3
122}
123
124; Function Attrs: nounwind readonly
125define fastcc <256 x double> @vgt_vvssml(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3) {
126; CHECK-LABEL: vgt_vvssml:
127; CHECK:       # %bb.0:
128; CHECK-NEXT:    lea %s2, 256
129; CHECK-NEXT:    lvl %s2
130; CHECK-NEXT:    vgt %v0, %v0, %s0, %s1, %vm1
131; CHECK-NEXT:    b.l.t (, %s10)
132  %5 = tail call fast <256 x double> @llvm.ve.vl.vgt.vvssml(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, i32 256)
133  ret <256 x double> %5
134}
135
136; Function Attrs: nounwind readonly
137declare <256 x double> @llvm.ve.vl.vgt.vvssml(<256 x double>, i64, i64, <256 x i1>, i32)
138
139; Function Attrs: nounwind readonly
140define fastcc <256 x double> @vgt_vvssmvl(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, <256 x double> %4) {
141; CHECK-LABEL: vgt_vvssmvl:
142; CHECK:       # %bb.0:
143; CHECK-NEXT:    lea %s2, 128
144; CHECK-NEXT:    lvl %s2
145; CHECK-NEXT:    vgt %v1, %v0, %s0, %s1, %vm1
146; CHECK-NEXT:    lea %s16, 256
147; CHECK-NEXT:    lvl %s16
148; CHECK-NEXT:    vor %v0, (0)1, %v1
149; CHECK-NEXT:    b.l.t (, %s10)
150  %6 = tail call fast <256 x double> @llvm.ve.vl.vgt.vvssmvl(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, <256 x double> %4, i32 128)
151  ret <256 x double> %6
152}
153
154; Function Attrs: nounwind readonly
155declare <256 x double> @llvm.ve.vl.vgt.vvssmvl(<256 x double>, i64, i64, <256 x i1>, <256 x double>, i32)
156
157; Function Attrs: nounwind readonly
158define fastcc <256 x double> @vgt_vvssml_imm_1(<256 x double> %0, i64 %1, <256 x i1> %2) {
159; CHECK-LABEL: vgt_vvssml_imm_1:
160; CHECK:       # %bb.0:
161; CHECK-NEXT:    lea %s1, 256
162; CHECK-NEXT:    lvl %s1
163; CHECK-NEXT:    vgt %v0, %v0, %s0, 0, %vm1
164; CHECK-NEXT:    b.l.t (, %s10)
165  %4 = tail call fast <256 x double> @llvm.ve.vl.vgt.vvssml(<256 x double> %0, i64 %1, i64 0, <256 x i1> %2, i32 256)
166  ret <256 x double> %4
167}
168
169; Function Attrs: nounwind readonly
170define fastcc <256 x double> @vgt_vvssmvl_imm_1(<256 x double> %0, i64 %1, <256 x i1> %2, <256 x double> %3) {
171; CHECK-LABEL: vgt_vvssmvl_imm_1:
172; CHECK:       # %bb.0:
173; CHECK-NEXT:    lea %s1, 128
174; CHECK-NEXT:    lvl %s1
175; CHECK-NEXT:    vgt %v1, %v0, %s0, 0, %vm1
176; CHECK-NEXT:    lea %s16, 256
177; CHECK-NEXT:    lvl %s16
178; CHECK-NEXT:    vor %v0, (0)1, %v1
179; CHECK-NEXT:    b.l.t (, %s10)
180  %5 = tail call fast <256 x double> @llvm.ve.vl.vgt.vvssmvl(<256 x double> %0, i64 %1, i64 0, <256 x i1> %2, <256 x double> %3, i32 128)
181  ret <256 x double> %5
182}
183
184; Function Attrs: nounwind readonly
185define fastcc <256 x double> @vgt_vvssml_imm_2(<256 x double> %0, i64 %1, <256 x i1> %2) {
186; CHECK-LABEL: vgt_vvssml_imm_2:
187; CHECK:       # %bb.0:
188; CHECK-NEXT:    lea %s1, 256
189; CHECK-NEXT:    lvl %s1
190; CHECK-NEXT:    vgt %v0, %v0, 8, %s0, %vm1
191; CHECK-NEXT:    b.l.t (, %s10)
192  %4 = tail call fast <256 x double> @llvm.ve.vl.vgt.vvssml(<256 x double> %0, i64 8, i64 %1, <256 x i1> %2, i32 256)
193  ret <256 x double> %4
194}
195
196; Function Attrs: nounwind readonly
197define fastcc <256 x double> @vgt_vvssmvl_imm_2(<256 x double> %0, i64 %1, <256 x i1> %2, <256 x double> %3) {
198; CHECK-LABEL: vgt_vvssmvl_imm_2:
199; CHECK:       # %bb.0:
200; CHECK-NEXT:    lea %s1, 128
201; CHECK-NEXT:    lvl %s1
202; CHECK-NEXT:    vgt %v1, %v0, 8, %s0, %vm1
203; CHECK-NEXT:    lea %s16, 256
204; CHECK-NEXT:    lvl %s16
205; CHECK-NEXT:    vor %v0, (0)1, %v1
206; CHECK-NEXT:    b.l.t (, %s10)
207  %5 = tail call fast <256 x double> @llvm.ve.vl.vgt.vvssmvl(<256 x double> %0, i64 8, i64 %1, <256 x i1> %2, <256 x double> %3, i32 128)
208  ret <256 x double> %5
209}
210
211; Function Attrs: nounwind readonly
212define fastcc <256 x double> @vgt_vvssml_imm_3(<256 x double> %0, <256 x i1> %1) {
213; CHECK-LABEL: vgt_vvssml_imm_3:
214; CHECK:       # %bb.0:
215; CHECK-NEXT:    lea %s0, 256
216; CHECK-NEXT:    lvl %s0
217; CHECK-NEXT:    vgt %v0, %v0, 8, 0, %vm1
218; CHECK-NEXT:    b.l.t (, %s10)
219  %3 = tail call fast <256 x double> @llvm.ve.vl.vgt.vvssml(<256 x double> %0, i64 8, i64 0, <256 x i1> %1, i32 256)
220  ret <256 x double> %3
221}
222
223; Function Attrs: nounwind readonly
224define fastcc <256 x double> @vgt_vvssmvl_imm_3(<256 x double> %0, <256 x i1> %1, <256 x double> %2) {
225; CHECK-LABEL: vgt_vvssmvl_imm_3:
226; CHECK:       # %bb.0:
227; CHECK-NEXT:    lea %s0, 128
228; CHECK-NEXT:    lvl %s0
229; CHECK-NEXT:    vgt %v1, %v0, 8, 0, %vm1
230; CHECK-NEXT:    lea %s16, 256
231; CHECK-NEXT:    lvl %s16
232; CHECK-NEXT:    vor %v0, (0)1, %v1
233; CHECK-NEXT:    b.l.t (, %s10)
234  %4 = tail call fast <256 x double> @llvm.ve.vl.vgt.vvssmvl(<256 x double> %0, i64 8, i64 0, <256 x i1> %1, <256 x double> %2, i32 128)
235  ret <256 x double> %4
236}
237
238; Function Attrs: nounwind readonly
239define fastcc <256 x double> @vgt_vvssl_no_imm_1(<256 x double> %0, i64 %1) {
240; CHECK-LABEL: vgt_vvssl_no_imm_1:
241; CHECK:       # %bb.0:
242; CHECK-NEXT:    lea %s1, 256
243; CHECK-NEXT:    or %s2, 8, (0)1
244; CHECK-NEXT:    lvl %s1
245; CHECK-NEXT:    vgt %v0, %v0, %s0, %s2
246; CHECK-NEXT:    b.l.t (, %s10)
247  %3 = tail call fast <256 x double> @llvm.ve.vl.vgt.vvssl(<256 x double> %0, i64 %1, i64 8, i32 256)
248  ret <256 x double> %3
249}
250
251; Function Attrs: nounwind readonly
252define fastcc <256 x double> @vgtnc_vvssl(<256 x double> %0, i64 %1, i64 %2) {
253; CHECK-LABEL: vgtnc_vvssl:
254; CHECK:       # %bb.0:
255; CHECK-NEXT:    lea %s2, 256
256; CHECK-NEXT:    lvl %s2
257; CHECK-NEXT:    vgt.nc %v0, %v0, %s0, %s1
258; CHECK-NEXT:    b.l.t (, %s10)
259  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtnc.vvssl(<256 x double> %0, i64 %1, i64 %2, i32 256)
260  ret <256 x double> %4
261}
262
263; Function Attrs: nounwind readonly
264declare <256 x double> @llvm.ve.vl.vgtnc.vvssl(<256 x double>, i64, i64, i32)
265
266; Function Attrs: nounwind readonly
267define fastcc <256 x double> @vgtnc_vvssvl(<256 x double> %0, i64 %1, i64 %2, <256 x double> %3) {
268; CHECK-LABEL: vgtnc_vvssvl:
269; CHECK:       # %bb.0:
270; CHECK-NEXT:    lea %s2, 128
271; CHECK-NEXT:    lvl %s2
272; CHECK-NEXT:    vgt.nc %v1, %v0, %s0, %s1
273; CHECK-NEXT:    lea %s16, 256
274; CHECK-NEXT:    lvl %s16
275; CHECK-NEXT:    vor %v0, (0)1, %v1
276; CHECK-NEXT:    b.l.t (, %s10)
277  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtnc.vvssvl(<256 x double> %0, i64 %1, i64 %2, <256 x double> %3, i32 128)
278  ret <256 x double> %5
279}
280
281; Function Attrs: nounwind readonly
282declare <256 x double> @llvm.ve.vl.vgtnc.vvssvl(<256 x double>, i64, i64, <256 x double>, i32)
283
284; Function Attrs: nounwind readonly
285define fastcc <256 x double> @vgtnc_vvssl_imm_1(<256 x double> %0, i64 %1) {
286; CHECK-LABEL: vgtnc_vvssl_imm_1:
287; CHECK:       # %bb.0:
288; CHECK-NEXT:    lea %s1, 256
289; CHECK-NEXT:    lvl %s1
290; CHECK-NEXT:    vgt.nc %v0, %v0, %s0, 0
291; CHECK-NEXT:    b.l.t (, %s10)
292  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtnc.vvssl(<256 x double> %0, i64 %1, i64 0, i32 256)
293  ret <256 x double> %3
294}
295
296; Function Attrs: nounwind readonly
297define fastcc <256 x double> @vgtnc_vvssvl_imm_1(<256 x double> %0, i64 %1, <256 x double> %2) {
298; CHECK-LABEL: vgtnc_vvssvl_imm_1:
299; CHECK:       # %bb.0:
300; CHECK-NEXT:    lea %s1, 128
301; CHECK-NEXT:    lvl %s1
302; CHECK-NEXT:    vgt.nc %v1, %v0, %s0, 0
303; CHECK-NEXT:    lea %s16, 256
304; CHECK-NEXT:    lvl %s16
305; CHECK-NEXT:    vor %v0, (0)1, %v1
306; CHECK-NEXT:    b.l.t (, %s10)
307  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtnc.vvssvl(<256 x double> %0, i64 %1, i64 0, <256 x double> %2, i32 128)
308  ret <256 x double> %4
309}
310
311; Function Attrs: nounwind readonly
312define fastcc <256 x double> @vgtnc_vvssl_imm_2(<256 x double> %0, i64 %1) {
313; CHECK-LABEL: vgtnc_vvssl_imm_2:
314; CHECK:       # %bb.0:
315; CHECK-NEXT:    lea %s1, 256
316; CHECK-NEXT:    lvl %s1
317; CHECK-NEXT:    vgt.nc %v0, %v0, 8, %s0
318; CHECK-NEXT:    b.l.t (, %s10)
319  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtnc.vvssl(<256 x double> %0, i64 8, i64 %1, i32 256)
320  ret <256 x double> %3
321}
322
323; Function Attrs: nounwind readonly
324define fastcc <256 x double> @vgtnc_vvssvl_imm_2(<256 x double> %0, i64 %1, <256 x double> %2) {
325; CHECK-LABEL: vgtnc_vvssvl_imm_2:
326; CHECK:       # %bb.0:
327; CHECK-NEXT:    lea %s1, 128
328; CHECK-NEXT:    lvl %s1
329; CHECK-NEXT:    vgt.nc %v1, %v0, 8, %s0
330; CHECK-NEXT:    lea %s16, 256
331; CHECK-NEXT:    lvl %s16
332; CHECK-NEXT:    vor %v0, (0)1, %v1
333; CHECK-NEXT:    b.l.t (, %s10)
334  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtnc.vvssvl(<256 x double> %0, i64 8, i64 %1, <256 x double> %2, i32 128)
335  ret <256 x double> %4
336}
337
338; Function Attrs: nounwind readonly
339define fastcc <256 x double> @vgtnc_vvssl_imm_3(<256 x double> %0) {
340; CHECK-LABEL: vgtnc_vvssl_imm_3:
341; CHECK:       # %bb.0:
342; CHECK-NEXT:    lea %s0, 256
343; CHECK-NEXT:    lvl %s0
344; CHECK-NEXT:    vgt.nc %v0, %v0, 8, 0
345; CHECK-NEXT:    b.l.t (, %s10)
346  %2 = tail call fast <256 x double> @llvm.ve.vl.vgtnc.vvssl(<256 x double> %0, i64 8, i64 0, i32 256)
347  ret <256 x double> %2
348}
349
350; Function Attrs: nounwind readonly
351define fastcc <256 x double> @vgtnc_vvssvl_imm_3(<256 x double> %0, <256 x double> %1) {
352; CHECK-LABEL: vgtnc_vvssvl_imm_3:
353; CHECK:       # %bb.0:
354; CHECK-NEXT:    lea %s0, 128
355; CHECK-NEXT:    lvl %s0
356; CHECK-NEXT:    vgt.nc %v1, %v0, 8, 0
357; CHECK-NEXT:    lea %s16, 256
358; CHECK-NEXT:    lvl %s16
359; CHECK-NEXT:    vor %v0, (0)1, %v1
360; CHECK-NEXT:    b.l.t (, %s10)
361  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtnc.vvssvl(<256 x double> %0, i64 8, i64 0, <256 x double> %1, i32 128)
362  ret <256 x double> %3
363}
364
365; Function Attrs: nounwind readonly
366define fastcc <256 x double> @vgtnc_vvssml(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3) {
367; CHECK-LABEL: vgtnc_vvssml:
368; CHECK:       # %bb.0:
369; CHECK-NEXT:    lea %s2, 256
370; CHECK-NEXT:    lvl %s2
371; CHECK-NEXT:    vgt.nc %v0, %v0, %s0, %s1, %vm1
372; CHECK-NEXT:    b.l.t (, %s10)
373  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtnc.vvssml(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, i32 256)
374  ret <256 x double> %5
375}
376
377; Function Attrs: nounwind readonly
378declare <256 x double> @llvm.ve.vl.vgtnc.vvssml(<256 x double>, i64, i64, <256 x i1>, i32)
379
380; Function Attrs: nounwind readonly
381define fastcc <256 x double> @vgtnc_vvssmvl(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, <256 x double> %4) {
382; CHECK-LABEL: vgtnc_vvssmvl:
383; CHECK:       # %bb.0:
384; CHECK-NEXT:    lea %s2, 128
385; CHECK-NEXT:    lvl %s2
386; CHECK-NEXT:    vgt.nc %v1, %v0, %s0, %s1, %vm1
387; CHECK-NEXT:    lea %s16, 256
388; CHECK-NEXT:    lvl %s16
389; CHECK-NEXT:    vor %v0, (0)1, %v1
390; CHECK-NEXT:    b.l.t (, %s10)
391  %6 = tail call fast <256 x double> @llvm.ve.vl.vgtnc.vvssmvl(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, <256 x double> %4, i32 128)
392  ret <256 x double> %6
393}
394
395; Function Attrs: nounwind readonly
396declare <256 x double> @llvm.ve.vl.vgtnc.vvssmvl(<256 x double>, i64, i64, <256 x i1>, <256 x double>, i32)
397
398; Function Attrs: nounwind readonly
399define fastcc <256 x double> @vgtnc_vvssml_imm_1(<256 x double> %0, i64 %1, <256 x i1> %2) {
400; CHECK-LABEL: vgtnc_vvssml_imm_1:
401; CHECK:       # %bb.0:
402; CHECK-NEXT:    lea %s1, 256
403; CHECK-NEXT:    lvl %s1
404; CHECK-NEXT:    vgt.nc %v0, %v0, %s0, 0, %vm1
405; CHECK-NEXT:    b.l.t (, %s10)
406  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtnc.vvssml(<256 x double> %0, i64 %1, i64 0, <256 x i1> %2, i32 256)
407  ret <256 x double> %4
408}
409
410; Function Attrs: nounwind readonly
411define fastcc <256 x double> @vgtnc_vvssmvl_imm_1(<256 x double> %0, i64 %1, <256 x i1> %2, <256 x double> %3) {
412; CHECK-LABEL: vgtnc_vvssmvl_imm_1:
413; CHECK:       # %bb.0:
414; CHECK-NEXT:    lea %s1, 128
415; CHECK-NEXT:    lvl %s1
416; CHECK-NEXT:    vgt.nc %v1, %v0, %s0, 0, %vm1
417; CHECK-NEXT:    lea %s16, 256
418; CHECK-NEXT:    lvl %s16
419; CHECK-NEXT:    vor %v0, (0)1, %v1
420; CHECK-NEXT:    b.l.t (, %s10)
421  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtnc.vvssmvl(<256 x double> %0, i64 %1, i64 0, <256 x i1> %2, <256 x double> %3, i32 128)
422  ret <256 x double> %5
423}
424
425; Function Attrs: nounwind readonly
426define fastcc <256 x double> @vgtnc_vvssml_imm_2(<256 x double> %0, i64 %1, <256 x i1> %2) {
427; CHECK-LABEL: vgtnc_vvssml_imm_2:
428; CHECK:       # %bb.0:
429; CHECK-NEXT:    lea %s1, 256
430; CHECK-NEXT:    lvl %s1
431; CHECK-NEXT:    vgt.nc %v0, %v0, 8, %s0, %vm1
432; CHECK-NEXT:    b.l.t (, %s10)
433  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtnc.vvssml(<256 x double> %0, i64 8, i64 %1, <256 x i1> %2, i32 256)
434  ret <256 x double> %4
435}
436
437; Function Attrs: nounwind readonly
438define fastcc <256 x double> @vgtnc_vvssmvl_imm_2(<256 x double> %0, i64 %1, <256 x i1> %2, <256 x double> %3) {
439; CHECK-LABEL: vgtnc_vvssmvl_imm_2:
440; CHECK:       # %bb.0:
441; CHECK-NEXT:    lea %s1, 128
442; CHECK-NEXT:    lvl %s1
443; CHECK-NEXT:    vgt.nc %v1, %v0, 8, %s0, %vm1
444; CHECK-NEXT:    lea %s16, 256
445; CHECK-NEXT:    lvl %s16
446; CHECK-NEXT:    vor %v0, (0)1, %v1
447; CHECK-NEXT:    b.l.t (, %s10)
448  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtnc.vvssmvl(<256 x double> %0, i64 8, i64 %1, <256 x i1> %2, <256 x double> %3, i32 128)
449  ret <256 x double> %5
450}
451
452; Function Attrs: nounwind readonly
453define fastcc <256 x double> @vgtnc_vvssml_imm_3(<256 x double> %0, <256 x i1> %1) {
454; CHECK-LABEL: vgtnc_vvssml_imm_3:
455; CHECK:       # %bb.0:
456; CHECK-NEXT:    lea %s0, 256
457; CHECK-NEXT:    lvl %s0
458; CHECK-NEXT:    vgt.nc %v0, %v0, 8, 0, %vm1
459; CHECK-NEXT:    b.l.t (, %s10)
460  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtnc.vvssml(<256 x double> %0, i64 8, i64 0, <256 x i1> %1, i32 256)
461  ret <256 x double> %3
462}
463
464; Function Attrs: nounwind readonly
465define fastcc <256 x double> @vgtnc_vvssmvl_imm_3(<256 x double> %0, <256 x i1> %1, <256 x double> %2) {
466; CHECK-LABEL: vgtnc_vvssmvl_imm_3:
467; CHECK:       # %bb.0:
468; CHECK-NEXT:    lea %s0, 128
469; CHECK-NEXT:    lvl %s0
470; CHECK-NEXT:    vgt.nc %v1, %v0, 8, 0, %vm1
471; CHECK-NEXT:    lea %s16, 256
472; CHECK-NEXT:    lvl %s16
473; CHECK-NEXT:    vor %v0, (0)1, %v1
474; CHECK-NEXT:    b.l.t (, %s10)
475  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtnc.vvssmvl(<256 x double> %0, i64 8, i64 0, <256 x i1> %1, <256 x double> %2, i32 128)
476  ret <256 x double> %4
477}
478
479; Function Attrs: nounwind readonly
480define fastcc <256 x double> @vgtnc_vvssl_no_imm_1(<256 x double> %0, i64 %1) {
481; CHECK-LABEL: vgtnc_vvssl_no_imm_1:
482; CHECK:       # %bb.0:
483; CHECK-NEXT:    lea %s1, 256
484; CHECK-NEXT:    or %s2, 8, (0)1
485; CHECK-NEXT:    lvl %s1
486; CHECK-NEXT:    vgt.nc %v0, %v0, %s0, %s2
487; CHECK-NEXT:    b.l.t (, %s10)
488  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtnc.vvssl(<256 x double> %0, i64 %1, i64 8, i32 256)
489  ret <256 x double> %3
490}
491
492; Function Attrs: nounwind readonly
493define fastcc <256 x double> @vgtu_vvssl(<256 x double> %0, i64 %1, i64 %2) {
494; CHECK-LABEL: vgtu_vvssl:
495; CHECK:       # %bb.0:
496; CHECK-NEXT:    lea %s2, 256
497; CHECK-NEXT:    lvl %s2
498; CHECK-NEXT:    vgtu %v0, %v0, %s0, %s1
499; CHECK-NEXT:    b.l.t (, %s10)
500  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtu.vvssl(<256 x double> %0, i64 %1, i64 %2, i32 256)
501  ret <256 x double> %4
502}
503
504; Function Attrs: nounwind readonly
505declare <256 x double> @llvm.ve.vl.vgtu.vvssl(<256 x double>, i64, i64, i32)
506
507; Function Attrs: nounwind readonly
508define fastcc <256 x double> @vgtu_vvssvl(<256 x double> %0, i64 %1, i64 %2, <256 x double> %3) {
509; CHECK-LABEL: vgtu_vvssvl:
510; CHECK:       # %bb.0:
511; CHECK-NEXT:    lea %s2, 128
512; CHECK-NEXT:    lvl %s2
513; CHECK-NEXT:    vgtu %v1, %v0, %s0, %s1
514; CHECK-NEXT:    lea %s16, 256
515; CHECK-NEXT:    lvl %s16
516; CHECK-NEXT:    vor %v0, (0)1, %v1
517; CHECK-NEXT:    b.l.t (, %s10)
518  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtu.vvssvl(<256 x double> %0, i64 %1, i64 %2, <256 x double> %3, i32 128)
519  ret <256 x double> %5
520}
521
522; Function Attrs: nounwind readonly
523declare <256 x double> @llvm.ve.vl.vgtu.vvssvl(<256 x double>, i64, i64, <256 x double>, i32)
524
525; Function Attrs: nounwind readonly
526define fastcc <256 x double> @vgtu_vvssl_imm_1(<256 x double> %0, i64 %1) {
527; CHECK-LABEL: vgtu_vvssl_imm_1:
528; CHECK:       # %bb.0:
529; CHECK-NEXT:    lea %s1, 256
530; CHECK-NEXT:    lvl %s1
531; CHECK-NEXT:    vgtu %v0, %v0, %s0, 0
532; CHECK-NEXT:    b.l.t (, %s10)
533  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtu.vvssl(<256 x double> %0, i64 %1, i64 0, i32 256)
534  ret <256 x double> %3
535}
536
537; Function Attrs: nounwind readonly
538define fastcc <256 x double> @vgtu_vvssvl_imm_1(<256 x double> %0, i64 %1, <256 x double> %2) {
539; CHECK-LABEL: vgtu_vvssvl_imm_1:
540; CHECK:       # %bb.0:
541; CHECK-NEXT:    lea %s1, 128
542; CHECK-NEXT:    lvl %s1
543; CHECK-NEXT:    vgtu %v1, %v0, %s0, 0
544; CHECK-NEXT:    lea %s16, 256
545; CHECK-NEXT:    lvl %s16
546; CHECK-NEXT:    vor %v0, (0)1, %v1
547; CHECK-NEXT:    b.l.t (, %s10)
548  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtu.vvssvl(<256 x double> %0, i64 %1, i64 0, <256 x double> %2, i32 128)
549  ret <256 x double> %4
550}
551
552; Function Attrs: nounwind readonly
553define fastcc <256 x double> @vgtu_vvssl_imm_2(<256 x double> %0, i64 %1) {
554; CHECK-LABEL: vgtu_vvssl_imm_2:
555; CHECK:       # %bb.0:
556; CHECK-NEXT:    lea %s1, 256
557; CHECK-NEXT:    lvl %s1
558; CHECK-NEXT:    vgtu %v0, %v0, 8, %s0
559; CHECK-NEXT:    b.l.t (, %s10)
560  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtu.vvssl(<256 x double> %0, i64 8, i64 %1, i32 256)
561  ret <256 x double> %3
562}
563
564; Function Attrs: nounwind readonly
565define fastcc <256 x double> @vgtu_vvssvl_imm_2(<256 x double> %0, i64 %1, <256 x double> %2) {
566; CHECK-LABEL: vgtu_vvssvl_imm_2:
567; CHECK:       # %bb.0:
568; CHECK-NEXT:    lea %s1, 128
569; CHECK-NEXT:    lvl %s1
570; CHECK-NEXT:    vgtu %v1, %v0, 8, %s0
571; CHECK-NEXT:    lea %s16, 256
572; CHECK-NEXT:    lvl %s16
573; CHECK-NEXT:    vor %v0, (0)1, %v1
574; CHECK-NEXT:    b.l.t (, %s10)
575  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtu.vvssvl(<256 x double> %0, i64 8, i64 %1, <256 x double> %2, i32 128)
576  ret <256 x double> %4
577}
578
579; Function Attrs: nounwind readonly
580define fastcc <256 x double> @vgtu_vvssl_imm_3(<256 x double> %0) {
581; CHECK-LABEL: vgtu_vvssl_imm_3:
582; CHECK:       # %bb.0:
583; CHECK-NEXT:    lea %s0, 256
584; CHECK-NEXT:    lvl %s0
585; CHECK-NEXT:    vgtu %v0, %v0, 8, 0
586; CHECK-NEXT:    b.l.t (, %s10)
587  %2 = tail call fast <256 x double> @llvm.ve.vl.vgtu.vvssl(<256 x double> %0, i64 8, i64 0, i32 256)
588  ret <256 x double> %2
589}
590
591; Function Attrs: nounwind readonly
592define fastcc <256 x double> @vgtu_vvssvl_imm_3(<256 x double> %0, <256 x double> %1) {
593; CHECK-LABEL: vgtu_vvssvl_imm_3:
594; CHECK:       # %bb.0:
595; CHECK-NEXT:    lea %s0, 128
596; CHECK-NEXT:    lvl %s0
597; CHECK-NEXT:    vgtu %v1, %v0, 8, 0
598; CHECK-NEXT:    lea %s16, 256
599; CHECK-NEXT:    lvl %s16
600; CHECK-NEXT:    vor %v0, (0)1, %v1
601; CHECK-NEXT:    b.l.t (, %s10)
602  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtu.vvssvl(<256 x double> %0, i64 8, i64 0, <256 x double> %1, i32 128)
603  ret <256 x double> %3
604}
605
606; Function Attrs: nounwind readonly
607define fastcc <256 x double> @vgtu_vvssml(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3) {
608; CHECK-LABEL: vgtu_vvssml:
609; CHECK:       # %bb.0:
610; CHECK-NEXT:    lea %s2, 256
611; CHECK-NEXT:    lvl %s2
612; CHECK-NEXT:    vgtu %v0, %v0, %s0, %s1, %vm1
613; CHECK-NEXT:    b.l.t (, %s10)
614  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtu.vvssml(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, i32 256)
615  ret <256 x double> %5
616}
617
618; Function Attrs: nounwind readonly
619declare <256 x double> @llvm.ve.vl.vgtu.vvssml(<256 x double>, i64, i64, <256 x i1>, i32)
620
621; Function Attrs: nounwind readonly
622define fastcc <256 x double> @vgtu_vvssmvl(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, <256 x double> %4) {
623; CHECK-LABEL: vgtu_vvssmvl:
624; CHECK:       # %bb.0:
625; CHECK-NEXT:    lea %s2, 128
626; CHECK-NEXT:    lvl %s2
627; CHECK-NEXT:    vgtu %v1, %v0, %s0, %s1, %vm1
628; CHECK-NEXT:    lea %s16, 256
629; CHECK-NEXT:    lvl %s16
630; CHECK-NEXT:    vor %v0, (0)1, %v1
631; CHECK-NEXT:    b.l.t (, %s10)
632  %6 = tail call fast <256 x double> @llvm.ve.vl.vgtu.vvssmvl(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, <256 x double> %4, i32 128)
633  ret <256 x double> %6
634}
635
636; Function Attrs: nounwind readonly
637declare <256 x double> @llvm.ve.vl.vgtu.vvssmvl(<256 x double>, i64, i64, <256 x i1>, <256 x double>, i32)
638
639; Function Attrs: nounwind readonly
640define fastcc <256 x double> @vgtu_vvssml_imm_1(<256 x double> %0, i64 %1, <256 x i1> %2) {
641; CHECK-LABEL: vgtu_vvssml_imm_1:
642; CHECK:       # %bb.0:
643; CHECK-NEXT:    lea %s1, 256
644; CHECK-NEXT:    lvl %s1
645; CHECK-NEXT:    vgtu %v0, %v0, %s0, 0, %vm1
646; CHECK-NEXT:    b.l.t (, %s10)
647  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtu.vvssml(<256 x double> %0, i64 %1, i64 0, <256 x i1> %2, i32 256)
648  ret <256 x double> %4
649}
650
651; Function Attrs: nounwind readonly
652define fastcc <256 x double> @vgtu_vvssmvl_imm_1(<256 x double> %0, i64 %1, <256 x i1> %2, <256 x double> %3) {
653; CHECK-LABEL: vgtu_vvssmvl_imm_1:
654; CHECK:       # %bb.0:
655; CHECK-NEXT:    lea %s1, 128
656; CHECK-NEXT:    lvl %s1
657; CHECK-NEXT:    vgtu %v1, %v0, %s0, 0, %vm1
658; CHECK-NEXT:    lea %s16, 256
659; CHECK-NEXT:    lvl %s16
660; CHECK-NEXT:    vor %v0, (0)1, %v1
661; CHECK-NEXT:    b.l.t (, %s10)
662  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtu.vvssmvl(<256 x double> %0, i64 %1, i64 0, <256 x i1> %2, <256 x double> %3, i32 128)
663  ret <256 x double> %5
664}
665
666; Function Attrs: nounwind readonly
667define fastcc <256 x double> @vgtu_vvssml_imm_2(<256 x double> %0, i64 %1, <256 x i1> %2) {
668; CHECK-LABEL: vgtu_vvssml_imm_2:
669; CHECK:       # %bb.0:
670; CHECK-NEXT:    lea %s1, 256
671; CHECK-NEXT:    lvl %s1
672; CHECK-NEXT:    vgtu %v0, %v0, 8, %s0, %vm1
673; CHECK-NEXT:    b.l.t (, %s10)
674  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtu.vvssml(<256 x double> %0, i64 8, i64 %1, <256 x i1> %2, i32 256)
675  ret <256 x double> %4
676}
677
678; Function Attrs: nounwind readonly
679define fastcc <256 x double> @vgtu_vvssmvl_imm_2(<256 x double> %0, i64 %1, <256 x i1> %2, <256 x double> %3) {
680; CHECK-LABEL: vgtu_vvssmvl_imm_2:
681; CHECK:       # %bb.0:
682; CHECK-NEXT:    lea %s1, 128
683; CHECK-NEXT:    lvl %s1
684; CHECK-NEXT:    vgtu %v1, %v0, 8, %s0, %vm1
685; CHECK-NEXT:    lea %s16, 256
686; CHECK-NEXT:    lvl %s16
687; CHECK-NEXT:    vor %v0, (0)1, %v1
688; CHECK-NEXT:    b.l.t (, %s10)
689  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtu.vvssmvl(<256 x double> %0, i64 8, i64 %1, <256 x i1> %2, <256 x double> %3, i32 128)
690  ret <256 x double> %5
691}
692
693; Function Attrs: nounwind readonly
694define fastcc <256 x double> @vgtu_vvssml_imm_3(<256 x double> %0, <256 x i1> %1) {
695; CHECK-LABEL: vgtu_vvssml_imm_3:
696; CHECK:       # %bb.0:
697; CHECK-NEXT:    lea %s0, 256
698; CHECK-NEXT:    lvl %s0
699; CHECK-NEXT:    vgtu %v0, %v0, 8, 0, %vm1
700; CHECK-NEXT:    b.l.t (, %s10)
701  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtu.vvssml(<256 x double> %0, i64 8, i64 0, <256 x i1> %1, i32 256)
702  ret <256 x double> %3
703}
704
705; Function Attrs: nounwind readonly
706define fastcc <256 x double> @vgtu_vvssmvl_imm_3(<256 x double> %0, <256 x i1> %1, <256 x double> %2) {
707; CHECK-LABEL: vgtu_vvssmvl_imm_3:
708; CHECK:       # %bb.0:
709; CHECK-NEXT:    lea %s0, 128
710; CHECK-NEXT:    lvl %s0
711; CHECK-NEXT:    vgtu %v1, %v0, 8, 0, %vm1
712; CHECK-NEXT:    lea %s16, 256
713; CHECK-NEXT:    lvl %s16
714; CHECK-NEXT:    vor %v0, (0)1, %v1
715; CHECK-NEXT:    b.l.t (, %s10)
716  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtu.vvssmvl(<256 x double> %0, i64 8, i64 0, <256 x i1> %1, <256 x double> %2, i32 128)
717  ret <256 x double> %4
718}
719
720; Function Attrs: nounwind readonly
721define fastcc <256 x double> @vgtu_vvssl_no_imm_1(<256 x double> %0, i64 %1) {
722; CHECK-LABEL: vgtu_vvssl_no_imm_1:
723; CHECK:       # %bb.0:
724; CHECK-NEXT:    lea %s1, 256
725; CHECK-NEXT:    or %s2, 8, (0)1
726; CHECK-NEXT:    lvl %s1
727; CHECK-NEXT:    vgtu %v0, %v0, %s0, %s2
728; CHECK-NEXT:    b.l.t (, %s10)
729  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtu.vvssl(<256 x double> %0, i64 %1, i64 8, i32 256)
730  ret <256 x double> %3
731}
732
733; Function Attrs: nounwind readonly
734define fastcc <256 x double> @vgtunc_vvssl(<256 x double> %0, i64 %1, i64 %2) {
735; CHECK-LABEL: vgtunc_vvssl:
736; CHECK:       # %bb.0:
737; CHECK-NEXT:    lea %s2, 256
738; CHECK-NEXT:    lvl %s2
739; CHECK-NEXT:    vgtu.nc %v0, %v0, %s0, %s1
740; CHECK-NEXT:    b.l.t (, %s10)
741  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtunc.vvssl(<256 x double> %0, i64 %1, i64 %2, i32 256)
742  ret <256 x double> %4
743}
744
745; Function Attrs: nounwind readonly
746declare <256 x double> @llvm.ve.vl.vgtunc.vvssl(<256 x double>, i64, i64, i32)
747
748; Function Attrs: nounwind readonly
749define fastcc <256 x double> @vgtunc_vvssvl(<256 x double> %0, i64 %1, i64 %2, <256 x double> %3) {
750; CHECK-LABEL: vgtunc_vvssvl:
751; CHECK:       # %bb.0:
752; CHECK-NEXT:    lea %s2, 128
753; CHECK-NEXT:    lvl %s2
754; CHECK-NEXT:    vgtu.nc %v1, %v0, %s0, %s1
755; CHECK-NEXT:    lea %s16, 256
756; CHECK-NEXT:    lvl %s16
757; CHECK-NEXT:    vor %v0, (0)1, %v1
758; CHECK-NEXT:    b.l.t (, %s10)
759  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtunc.vvssvl(<256 x double> %0, i64 %1, i64 %2, <256 x double> %3, i32 128)
760  ret <256 x double> %5
761}
762
763; Function Attrs: nounwind readonly
764declare <256 x double> @llvm.ve.vl.vgtunc.vvssvl(<256 x double>, i64, i64, <256 x double>, i32)
765
766; Function Attrs: nounwind readonly
767define fastcc <256 x double> @vgtunc_vvssl_imm_1(<256 x double> %0, i64 %1) {
768; CHECK-LABEL: vgtunc_vvssl_imm_1:
769; CHECK:       # %bb.0:
770; CHECK-NEXT:    lea %s1, 256
771; CHECK-NEXT:    lvl %s1
772; CHECK-NEXT:    vgtu.nc %v0, %v0, %s0, 0
773; CHECK-NEXT:    b.l.t (, %s10)
774  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtunc.vvssl(<256 x double> %0, i64 %1, i64 0, i32 256)
775  ret <256 x double> %3
776}
777
778; Function Attrs: nounwind readonly
779define fastcc <256 x double> @vgtunc_vvssvl_imm_1(<256 x double> %0, i64 %1, <256 x double> %2) {
780; CHECK-LABEL: vgtunc_vvssvl_imm_1:
781; CHECK:       # %bb.0:
782; CHECK-NEXT:    lea %s1, 128
783; CHECK-NEXT:    lvl %s1
784; CHECK-NEXT:    vgtu.nc %v1, %v0, %s0, 0
785; CHECK-NEXT:    lea %s16, 256
786; CHECK-NEXT:    lvl %s16
787; CHECK-NEXT:    vor %v0, (0)1, %v1
788; CHECK-NEXT:    b.l.t (, %s10)
789  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtunc.vvssvl(<256 x double> %0, i64 %1, i64 0, <256 x double> %2, i32 128)
790  ret <256 x double> %4
791}
792
793; Function Attrs: nounwind readonly
794define fastcc <256 x double> @vgtunc_vvssl_imm_2(<256 x double> %0, i64 %1) {
795; CHECK-LABEL: vgtunc_vvssl_imm_2:
796; CHECK:       # %bb.0:
797; CHECK-NEXT:    lea %s1, 256
798; CHECK-NEXT:    lvl %s1
799; CHECK-NEXT:    vgtu.nc %v0, %v0, 8, %s0
800; CHECK-NEXT:    b.l.t (, %s10)
801  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtunc.vvssl(<256 x double> %0, i64 8, i64 %1, i32 256)
802  ret <256 x double> %3
803}
804
805; Function Attrs: nounwind readonly
806define fastcc <256 x double> @vgtunc_vvssvl_imm_2(<256 x double> %0, i64 %1, <256 x double> %2) {
807; CHECK-LABEL: vgtunc_vvssvl_imm_2:
808; CHECK:       # %bb.0:
809; CHECK-NEXT:    lea %s1, 128
810; CHECK-NEXT:    lvl %s1
811; CHECK-NEXT:    vgtu.nc %v1, %v0, 8, %s0
812; CHECK-NEXT:    lea %s16, 256
813; CHECK-NEXT:    lvl %s16
814; CHECK-NEXT:    vor %v0, (0)1, %v1
815; CHECK-NEXT:    b.l.t (, %s10)
816  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtunc.vvssvl(<256 x double> %0, i64 8, i64 %1, <256 x double> %2, i32 128)
817  ret <256 x double> %4
818}
819
820; Function Attrs: nounwind readonly
821define fastcc <256 x double> @vgtunc_vvssl_imm_3(<256 x double> %0) {
822; CHECK-LABEL: vgtunc_vvssl_imm_3:
823; CHECK:       # %bb.0:
824; CHECK-NEXT:    lea %s0, 256
825; CHECK-NEXT:    lvl %s0
826; CHECK-NEXT:    vgtu.nc %v0, %v0, 8, 0
827; CHECK-NEXT:    b.l.t (, %s10)
828  %2 = tail call fast <256 x double> @llvm.ve.vl.vgtunc.vvssl(<256 x double> %0, i64 8, i64 0, i32 256)
829  ret <256 x double> %2
830}
831
832; Function Attrs: nounwind readonly
833define fastcc <256 x double> @vgtunc_vvssvl_imm_3(<256 x double> %0, <256 x double> %1) {
834; CHECK-LABEL: vgtunc_vvssvl_imm_3:
835; CHECK:       # %bb.0:
836; CHECK-NEXT:    lea %s0, 128
837; CHECK-NEXT:    lvl %s0
838; CHECK-NEXT:    vgtu.nc %v1, %v0, 8, 0
839; CHECK-NEXT:    lea %s16, 256
840; CHECK-NEXT:    lvl %s16
841; CHECK-NEXT:    vor %v0, (0)1, %v1
842; CHECK-NEXT:    b.l.t (, %s10)
843  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtunc.vvssvl(<256 x double> %0, i64 8, i64 0, <256 x double> %1, i32 128)
844  ret <256 x double> %3
845}
846
847; Function Attrs: nounwind readonly
848define fastcc <256 x double> @vgtunc_vvssml(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3) {
849; CHECK-LABEL: vgtunc_vvssml:
850; CHECK:       # %bb.0:
851; CHECK-NEXT:    lea %s2, 256
852; CHECK-NEXT:    lvl %s2
853; CHECK-NEXT:    vgtu.nc %v0, %v0, %s0, %s1, %vm1
854; CHECK-NEXT:    b.l.t (, %s10)
855  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtunc.vvssml(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, i32 256)
856  ret <256 x double> %5
857}
858
859; Function Attrs: nounwind readonly
860declare <256 x double> @llvm.ve.vl.vgtunc.vvssml(<256 x double>, i64, i64, <256 x i1>, i32)
861
862; Function Attrs: nounwind readonly
863define fastcc <256 x double> @vgtunc_vvssmvl(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, <256 x double> %4) {
864; CHECK-LABEL: vgtunc_vvssmvl:
865; CHECK:       # %bb.0:
866; CHECK-NEXT:    lea %s2, 128
867; CHECK-NEXT:    lvl %s2
868; CHECK-NEXT:    vgtu.nc %v1, %v0, %s0, %s1, %vm1
869; CHECK-NEXT:    lea %s16, 256
870; CHECK-NEXT:    lvl %s16
871; CHECK-NEXT:    vor %v0, (0)1, %v1
872; CHECK-NEXT:    b.l.t (, %s10)
873  %6 = tail call fast <256 x double> @llvm.ve.vl.vgtunc.vvssmvl(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, <256 x double> %4, i32 128)
874  ret <256 x double> %6
875}
876
877; Function Attrs: nounwind readonly
878declare <256 x double> @llvm.ve.vl.vgtunc.vvssmvl(<256 x double>, i64, i64, <256 x i1>, <256 x double>, i32)
879
880; Function Attrs: nounwind readonly
881define fastcc <256 x double> @vgtunc_vvssml_imm_1(<256 x double> %0, i64 %1, <256 x i1> %2) {
882; CHECK-LABEL: vgtunc_vvssml_imm_1:
883; CHECK:       # %bb.0:
884; CHECK-NEXT:    lea %s1, 256
885; CHECK-NEXT:    lvl %s1
886; CHECK-NEXT:    vgtu.nc %v0, %v0, %s0, 0, %vm1
887; CHECK-NEXT:    b.l.t (, %s10)
888  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtunc.vvssml(<256 x double> %0, i64 %1, i64 0, <256 x i1> %2, i32 256)
889  ret <256 x double> %4
890}
891
892; Function Attrs: nounwind readonly
893define fastcc <256 x double> @vgtunc_vvssmvl_imm_1(<256 x double> %0, i64 %1, <256 x i1> %2, <256 x double> %3) {
894; CHECK-LABEL: vgtunc_vvssmvl_imm_1:
895; CHECK:       # %bb.0:
896; CHECK-NEXT:    lea %s1, 128
897; CHECK-NEXT:    lvl %s1
898; CHECK-NEXT:    vgtu.nc %v1, %v0, %s0, 0, %vm1
899; CHECK-NEXT:    lea %s16, 256
900; CHECK-NEXT:    lvl %s16
901; CHECK-NEXT:    vor %v0, (0)1, %v1
902; CHECK-NEXT:    b.l.t (, %s10)
903  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtunc.vvssmvl(<256 x double> %0, i64 %1, i64 0, <256 x i1> %2, <256 x double> %3, i32 128)
904  ret <256 x double> %5
905}
906
907; Function Attrs: nounwind readonly
908define fastcc <256 x double> @vgtunc_vvssml_imm_2(<256 x double> %0, i64 %1, <256 x i1> %2) {
909; CHECK-LABEL: vgtunc_vvssml_imm_2:
910; CHECK:       # %bb.0:
911; CHECK-NEXT:    lea %s1, 256
912; CHECK-NEXT:    lvl %s1
913; CHECK-NEXT:    vgtu.nc %v0, %v0, 8, %s0, %vm1
914; CHECK-NEXT:    b.l.t (, %s10)
915  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtunc.vvssml(<256 x double> %0, i64 8, i64 %1, <256 x i1> %2, i32 256)
916  ret <256 x double> %4
917}
918
919; Function Attrs: nounwind readonly
920define fastcc <256 x double> @vgtunc_vvssmvl_imm_2(<256 x double> %0, i64 %1, <256 x i1> %2, <256 x double> %3) {
921; CHECK-LABEL: vgtunc_vvssmvl_imm_2:
922; CHECK:       # %bb.0:
923; CHECK-NEXT:    lea %s1, 128
924; CHECK-NEXT:    lvl %s1
925; CHECK-NEXT:    vgtu.nc %v1, %v0, 8, %s0, %vm1
926; CHECK-NEXT:    lea %s16, 256
927; CHECK-NEXT:    lvl %s16
928; CHECK-NEXT:    vor %v0, (0)1, %v1
929; CHECK-NEXT:    b.l.t (, %s10)
930  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtunc.vvssmvl(<256 x double> %0, i64 8, i64 %1, <256 x i1> %2, <256 x double> %3, i32 128)
931  ret <256 x double> %5
932}
933
934; Function Attrs: nounwind readonly
935define fastcc <256 x double> @vgtunc_vvssml_imm_3(<256 x double> %0, <256 x i1> %1) {
936; CHECK-LABEL: vgtunc_vvssml_imm_3:
937; CHECK:       # %bb.0:
938; CHECK-NEXT:    lea %s0, 256
939; CHECK-NEXT:    lvl %s0
940; CHECK-NEXT:    vgtu.nc %v0, %v0, 8, 0, %vm1
941; CHECK-NEXT:    b.l.t (, %s10)
942  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtunc.vvssml(<256 x double> %0, i64 8, i64 0, <256 x i1> %1, i32 256)
943  ret <256 x double> %3
944}
945
946; Function Attrs: nounwind readonly
947define fastcc <256 x double> @vgtunc_vvssmvl_imm_3(<256 x double> %0, <256 x i1> %1, <256 x double> %2) {
948; CHECK-LABEL: vgtunc_vvssmvl_imm_3:
949; CHECK:       # %bb.0:
950; CHECK-NEXT:    lea %s0, 128
951; CHECK-NEXT:    lvl %s0
952; CHECK-NEXT:    vgtu.nc %v1, %v0, 8, 0, %vm1
953; CHECK-NEXT:    lea %s16, 256
954; CHECK-NEXT:    lvl %s16
955; CHECK-NEXT:    vor %v0, (0)1, %v1
956; CHECK-NEXT:    b.l.t (, %s10)
957  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtunc.vvssmvl(<256 x double> %0, i64 8, i64 0, <256 x i1> %1, <256 x double> %2, i32 128)
958  ret <256 x double> %4
959}
960
961; Function Attrs: nounwind readonly
962define fastcc <256 x double> @vgtunc_vvssl_no_imm_1(<256 x double> %0, i64 %1) {
963; CHECK-LABEL: vgtunc_vvssl_no_imm_1:
964; CHECK:       # %bb.0:
965; CHECK-NEXT:    lea %s1, 256
966; CHECK-NEXT:    or %s2, 8, (0)1
967; CHECK-NEXT:    lvl %s1
968; CHECK-NEXT:    vgtu.nc %v0, %v0, %s0, %s2
969; CHECK-NEXT:    b.l.t (, %s10)
970  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtunc.vvssl(<256 x double> %0, i64 %1, i64 8, i32 256)
971  ret <256 x double> %3
972}
973
974; Function Attrs: nounwind readonly
975define fastcc <256 x double> @vgtlsx_vvssl(<256 x double> %0, i64 %1, i64 %2) {
976; CHECK-LABEL: vgtlsx_vvssl:
977; CHECK:       # %bb.0:
978; CHECK-NEXT:    lea %s2, 256
979; CHECK-NEXT:    lvl %s2
980; CHECK-NEXT:    vgtl.sx %v0, %v0, %s0, %s1
981; CHECK-NEXT:    b.l.t (, %s10)
982  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtlsx.vvssl(<256 x double> %0, i64 %1, i64 %2, i32 256)
983  ret <256 x double> %4
984}
985
986; Function Attrs: nounwind readonly
987declare <256 x double> @llvm.ve.vl.vgtlsx.vvssl(<256 x double>, i64, i64, i32)
988
989; Function Attrs: nounwind readonly
990define fastcc <256 x double> @vgtlsx_vvssvl(<256 x double> %0, i64 %1, i64 %2, <256 x double> %3) {
991; CHECK-LABEL: vgtlsx_vvssvl:
992; CHECK:       # %bb.0:
993; CHECK-NEXT:    lea %s2, 128
994; CHECK-NEXT:    lvl %s2
995; CHECK-NEXT:    vgtl.sx %v1, %v0, %s0, %s1
996; CHECK-NEXT:    lea %s16, 256
997; CHECK-NEXT:    lvl %s16
998; CHECK-NEXT:    vor %v0, (0)1, %v1
999; CHECK-NEXT:    b.l.t (, %s10)
1000  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtlsx.vvssvl(<256 x double> %0, i64 %1, i64 %2, <256 x double> %3, i32 128)
1001  ret <256 x double> %5
1002}
1003
1004; Function Attrs: nounwind readonly
1005declare <256 x double> @llvm.ve.vl.vgtlsx.vvssvl(<256 x double>, i64, i64, <256 x double>, i32)
1006
1007; Function Attrs: nounwind readonly
1008define fastcc <256 x double> @vgtlsx_vvssl_imm_1(<256 x double> %0, i64 %1) {
1009; CHECK-LABEL: vgtlsx_vvssl_imm_1:
1010; CHECK:       # %bb.0:
1011; CHECK-NEXT:    lea %s1, 256
1012; CHECK-NEXT:    lvl %s1
1013; CHECK-NEXT:    vgtl.sx %v0, %v0, %s0, 0
1014; CHECK-NEXT:    b.l.t (, %s10)
1015  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtlsx.vvssl(<256 x double> %0, i64 %1, i64 0, i32 256)
1016  ret <256 x double> %3
1017}
1018
1019; Function Attrs: nounwind readonly
1020define fastcc <256 x double> @vgtlsx_vvssvl_imm_1(<256 x double> %0, i64 %1, <256 x double> %2) {
1021; CHECK-LABEL: vgtlsx_vvssvl_imm_1:
1022; CHECK:       # %bb.0:
1023; CHECK-NEXT:    lea %s1, 128
1024; CHECK-NEXT:    lvl %s1
1025; CHECK-NEXT:    vgtl.sx %v1, %v0, %s0, 0
1026; CHECK-NEXT:    lea %s16, 256
1027; CHECK-NEXT:    lvl %s16
1028; CHECK-NEXT:    vor %v0, (0)1, %v1
1029; CHECK-NEXT:    b.l.t (, %s10)
1030  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtlsx.vvssvl(<256 x double> %0, i64 %1, i64 0, <256 x double> %2, i32 128)
1031  ret <256 x double> %4
1032}
1033
1034; Function Attrs: nounwind readonly
1035define fastcc <256 x double> @vgtlsx_vvssl_imm_2(<256 x double> %0, i64 %1) {
1036; CHECK-LABEL: vgtlsx_vvssl_imm_2:
1037; CHECK:       # %bb.0:
1038; CHECK-NEXT:    lea %s1, 256
1039; CHECK-NEXT:    lvl %s1
1040; CHECK-NEXT:    vgtl.sx %v0, %v0, 8, %s0
1041; CHECK-NEXT:    b.l.t (, %s10)
1042  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtlsx.vvssl(<256 x double> %0, i64 8, i64 %1, i32 256)
1043  ret <256 x double> %3
1044}
1045
1046; Function Attrs: nounwind readonly
1047define fastcc <256 x double> @vgtlsx_vvssvl_imm_2(<256 x double> %0, i64 %1, <256 x double> %2) {
1048; CHECK-LABEL: vgtlsx_vvssvl_imm_2:
1049; CHECK:       # %bb.0:
1050; CHECK-NEXT:    lea %s1, 128
1051; CHECK-NEXT:    lvl %s1
1052; CHECK-NEXT:    vgtl.sx %v1, %v0, 8, %s0
1053; CHECK-NEXT:    lea %s16, 256
1054; CHECK-NEXT:    lvl %s16
1055; CHECK-NEXT:    vor %v0, (0)1, %v1
1056; CHECK-NEXT:    b.l.t (, %s10)
1057  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtlsx.vvssvl(<256 x double> %0, i64 8, i64 %1, <256 x double> %2, i32 128)
1058  ret <256 x double> %4
1059}
1060
1061; Function Attrs: nounwind readonly
1062define fastcc <256 x double> @vgtlsx_vvssl_imm_3(<256 x double> %0) {
1063; CHECK-LABEL: vgtlsx_vvssl_imm_3:
1064; CHECK:       # %bb.0:
1065; CHECK-NEXT:    lea %s0, 256
1066; CHECK-NEXT:    lvl %s0
1067; CHECK-NEXT:    vgtl.sx %v0, %v0, 8, 0
1068; CHECK-NEXT:    b.l.t (, %s10)
1069  %2 = tail call fast <256 x double> @llvm.ve.vl.vgtlsx.vvssl(<256 x double> %0, i64 8, i64 0, i32 256)
1070  ret <256 x double> %2
1071}
1072
1073; Function Attrs: nounwind readonly
1074define fastcc <256 x double> @vgtlsx_vvssvl_imm_3(<256 x double> %0, <256 x double> %1) {
1075; CHECK-LABEL: vgtlsx_vvssvl_imm_3:
1076; CHECK:       # %bb.0:
1077; CHECK-NEXT:    lea %s0, 128
1078; CHECK-NEXT:    lvl %s0
1079; CHECK-NEXT:    vgtl.sx %v1, %v0, 8, 0
1080; CHECK-NEXT:    lea %s16, 256
1081; CHECK-NEXT:    lvl %s16
1082; CHECK-NEXT:    vor %v0, (0)1, %v1
1083; CHECK-NEXT:    b.l.t (, %s10)
1084  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtlsx.vvssvl(<256 x double> %0, i64 8, i64 0, <256 x double> %1, i32 128)
1085  ret <256 x double> %3
1086}
1087
1088; Function Attrs: nounwind readonly
1089define fastcc <256 x double> @vgtlsx_vvssml(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3) {
1090; CHECK-LABEL: vgtlsx_vvssml:
1091; CHECK:       # %bb.0:
1092; CHECK-NEXT:    lea %s2, 256
1093; CHECK-NEXT:    lvl %s2
1094; CHECK-NEXT:    vgtl.sx %v0, %v0, %s0, %s1, %vm1
1095; CHECK-NEXT:    b.l.t (, %s10)
1096  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtlsx.vvssml(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, i32 256)
1097  ret <256 x double> %5
1098}
1099
1100; Function Attrs: nounwind readonly
1101declare <256 x double> @llvm.ve.vl.vgtlsx.vvssml(<256 x double>, i64, i64, <256 x i1>, i32)
1102
1103; Function Attrs: nounwind readonly
1104define fastcc <256 x double> @vgtlsx_vvssmvl(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, <256 x double> %4) {
1105; CHECK-LABEL: vgtlsx_vvssmvl:
1106; CHECK:       # %bb.0:
1107; CHECK-NEXT:    lea %s2, 128
1108; CHECK-NEXT:    lvl %s2
1109; CHECK-NEXT:    vgtl.sx %v1, %v0, %s0, %s1, %vm1
1110; CHECK-NEXT:    lea %s16, 256
1111; CHECK-NEXT:    lvl %s16
1112; CHECK-NEXT:    vor %v0, (0)1, %v1
1113; CHECK-NEXT:    b.l.t (, %s10)
1114  %6 = tail call fast <256 x double> @llvm.ve.vl.vgtlsx.vvssmvl(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, <256 x double> %4, i32 128)
1115  ret <256 x double> %6
1116}
1117
1118; Function Attrs: nounwind readonly
1119declare <256 x double> @llvm.ve.vl.vgtlsx.vvssmvl(<256 x double>, i64, i64, <256 x i1>, <256 x double>, i32)
1120
1121; Function Attrs: nounwind readonly
1122define fastcc <256 x double> @vgtlsx_vvssml_imm_1(<256 x double> %0, i64 %1, <256 x i1> %2) {
1123; CHECK-LABEL: vgtlsx_vvssml_imm_1:
1124; CHECK:       # %bb.0:
1125; CHECK-NEXT:    lea %s1, 256
1126; CHECK-NEXT:    lvl %s1
1127; CHECK-NEXT:    vgtl.sx %v0, %v0, %s0, 0, %vm1
1128; CHECK-NEXT:    b.l.t (, %s10)
1129  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtlsx.vvssml(<256 x double> %0, i64 %1, i64 0, <256 x i1> %2, i32 256)
1130  ret <256 x double> %4
1131}
1132
1133; Function Attrs: nounwind readonly
1134define fastcc <256 x double> @vgtlsx_vvssmvl_imm_1(<256 x double> %0, i64 %1, <256 x i1> %2, <256 x double> %3) {
1135; CHECK-LABEL: vgtlsx_vvssmvl_imm_1:
1136; CHECK:       # %bb.0:
1137; CHECK-NEXT:    lea %s1, 128
1138; CHECK-NEXT:    lvl %s1
1139; CHECK-NEXT:    vgtl.sx %v1, %v0, %s0, 0, %vm1
1140; CHECK-NEXT:    lea %s16, 256
1141; CHECK-NEXT:    lvl %s16
1142; CHECK-NEXT:    vor %v0, (0)1, %v1
1143; CHECK-NEXT:    b.l.t (, %s10)
1144  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtlsx.vvssmvl(<256 x double> %0, i64 %1, i64 0, <256 x i1> %2, <256 x double> %3, i32 128)
1145  ret <256 x double> %5
1146}
1147
1148; Function Attrs: nounwind readonly
1149define fastcc <256 x double> @vgtlsx_vvssml_imm_2(<256 x double> %0, i64 %1, <256 x i1> %2) {
1150; CHECK-LABEL: vgtlsx_vvssml_imm_2:
1151; CHECK:       # %bb.0:
1152; CHECK-NEXT:    lea %s1, 256
1153; CHECK-NEXT:    lvl %s1
1154; CHECK-NEXT:    vgtl.sx %v0, %v0, 8, %s0, %vm1
1155; CHECK-NEXT:    b.l.t (, %s10)
1156  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtlsx.vvssml(<256 x double> %0, i64 8, i64 %1, <256 x i1> %2, i32 256)
1157  ret <256 x double> %4
1158}
1159
1160; Function Attrs: nounwind readonly
1161define fastcc <256 x double> @vgtlsx_vvssmvl_imm_2(<256 x double> %0, i64 %1, <256 x i1> %2, <256 x double> %3) {
1162; CHECK-LABEL: vgtlsx_vvssmvl_imm_2:
1163; CHECK:       # %bb.0:
1164; CHECK-NEXT:    lea %s1, 128
1165; CHECK-NEXT:    lvl %s1
1166; CHECK-NEXT:    vgtl.sx %v1, %v0, 8, %s0, %vm1
1167; CHECK-NEXT:    lea %s16, 256
1168; CHECK-NEXT:    lvl %s16
1169; CHECK-NEXT:    vor %v0, (0)1, %v1
1170; CHECK-NEXT:    b.l.t (, %s10)
1171  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtlsx.vvssmvl(<256 x double> %0, i64 8, i64 %1, <256 x i1> %2, <256 x double> %3, i32 128)
1172  ret <256 x double> %5
1173}
1174
1175; Function Attrs: nounwind readonly
1176define fastcc <256 x double> @vgtlsx_vvssml_imm_3(<256 x double> %0, <256 x i1> %1) {
1177; CHECK-LABEL: vgtlsx_vvssml_imm_3:
1178; CHECK:       # %bb.0:
1179; CHECK-NEXT:    lea %s0, 256
1180; CHECK-NEXT:    lvl %s0
1181; CHECK-NEXT:    vgtl.sx %v0, %v0, 8, 0, %vm1
1182; CHECK-NEXT:    b.l.t (, %s10)
1183  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtlsx.vvssml(<256 x double> %0, i64 8, i64 0, <256 x i1> %1, i32 256)
1184  ret <256 x double> %3
1185}
1186
1187; Function Attrs: nounwind readonly
1188define fastcc <256 x double> @vgtlsx_vvssmvl_imm_3(<256 x double> %0, <256 x i1> %1, <256 x double> %2) {
1189; CHECK-LABEL: vgtlsx_vvssmvl_imm_3:
1190; CHECK:       # %bb.0:
1191; CHECK-NEXT:    lea %s0, 128
1192; CHECK-NEXT:    lvl %s0
1193; CHECK-NEXT:    vgtl.sx %v1, %v0, 8, 0, %vm1
1194; CHECK-NEXT:    lea %s16, 256
1195; CHECK-NEXT:    lvl %s16
1196; CHECK-NEXT:    vor %v0, (0)1, %v1
1197; CHECK-NEXT:    b.l.t (, %s10)
1198  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtlsx.vvssmvl(<256 x double> %0, i64 8, i64 0, <256 x i1> %1, <256 x double> %2, i32 128)
1199  ret <256 x double> %4
1200}
1201
1202; Function Attrs: nounwind readonly
1203define fastcc <256 x double> @vgtlsx_vvssl_no_imm_1(<256 x double> %0, i64 %1) {
1204; CHECK-LABEL: vgtlsx_vvssl_no_imm_1:
1205; CHECK:       # %bb.0:
1206; CHECK-NEXT:    lea %s1, 256
1207; CHECK-NEXT:    or %s2, 8, (0)1
1208; CHECK-NEXT:    lvl %s1
1209; CHECK-NEXT:    vgtl.sx %v0, %v0, %s0, %s2
1210; CHECK-NEXT:    b.l.t (, %s10)
1211  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtlsx.vvssl(<256 x double> %0, i64 %1, i64 8, i32 256)
1212  ret <256 x double> %3
1213}
1214
1215; Function Attrs: nounwind readonly
1216define fastcc <256 x double> @vgtlsxnc_vvssl(<256 x double> %0, i64 %1, i64 %2) {
1217; CHECK-LABEL: vgtlsxnc_vvssl:
1218; CHECK:       # %bb.0:
1219; CHECK-NEXT:    lea %s2, 256
1220; CHECK-NEXT:    lvl %s2
1221; CHECK-NEXT:    vgtl.sx.nc %v0, %v0, %s0, %s1
1222; CHECK-NEXT:    b.l.t (, %s10)
1223  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtlsxnc.vvssl(<256 x double> %0, i64 %1, i64 %2, i32 256)
1224  ret <256 x double> %4
1225}
1226
1227; Function Attrs: nounwind readonly
1228declare <256 x double> @llvm.ve.vl.vgtlsxnc.vvssl(<256 x double>, i64, i64, i32)
1229
1230; Function Attrs: nounwind readonly
1231define fastcc <256 x double> @vgtlsxnc_vvssvl(<256 x double> %0, i64 %1, i64 %2, <256 x double> %3) {
1232; CHECK-LABEL: vgtlsxnc_vvssvl:
1233; CHECK:       # %bb.0:
1234; CHECK-NEXT:    lea %s2, 128
1235; CHECK-NEXT:    lvl %s2
1236; CHECK-NEXT:    vgtl.sx.nc %v1, %v0, %s0, %s1
1237; CHECK-NEXT:    lea %s16, 256
1238; CHECK-NEXT:    lvl %s16
1239; CHECK-NEXT:    vor %v0, (0)1, %v1
1240; CHECK-NEXT:    b.l.t (, %s10)
1241  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtlsxnc.vvssvl(<256 x double> %0, i64 %1, i64 %2, <256 x double> %3, i32 128)
1242  ret <256 x double> %5
1243}
1244
1245; Function Attrs: nounwind readonly
1246declare <256 x double> @llvm.ve.vl.vgtlsxnc.vvssvl(<256 x double>, i64, i64, <256 x double>, i32)
1247
1248; Function Attrs: nounwind readonly
1249define fastcc <256 x double> @vgtlsxnc_vvssl_imm_1(<256 x double> %0, i64 %1) {
1250; CHECK-LABEL: vgtlsxnc_vvssl_imm_1:
1251; CHECK:       # %bb.0:
1252; CHECK-NEXT:    lea %s1, 256
1253; CHECK-NEXT:    lvl %s1
1254; CHECK-NEXT:    vgtl.sx.nc %v0, %v0, %s0, 0
1255; CHECK-NEXT:    b.l.t (, %s10)
1256  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtlsxnc.vvssl(<256 x double> %0, i64 %1, i64 0, i32 256)
1257  ret <256 x double> %3
1258}
1259
1260; Function Attrs: nounwind readonly
1261define fastcc <256 x double> @vgtlsxnc_vvssvl_imm_1(<256 x double> %0, i64 %1, <256 x double> %2) {
1262; CHECK-LABEL: vgtlsxnc_vvssvl_imm_1:
1263; CHECK:       # %bb.0:
1264; CHECK-NEXT:    lea %s1, 128
1265; CHECK-NEXT:    lvl %s1
1266; CHECK-NEXT:    vgtl.sx.nc %v1, %v0, %s0, 0
1267; CHECK-NEXT:    lea %s16, 256
1268; CHECK-NEXT:    lvl %s16
1269; CHECK-NEXT:    vor %v0, (0)1, %v1
1270; CHECK-NEXT:    b.l.t (, %s10)
1271  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtlsxnc.vvssvl(<256 x double> %0, i64 %1, i64 0, <256 x double> %2, i32 128)
1272  ret <256 x double> %4
1273}
1274
1275; Function Attrs: nounwind readonly
1276define fastcc <256 x double> @vgtlsxnc_vvssl_imm_2(<256 x double> %0, i64 %1) {
1277; CHECK-LABEL: vgtlsxnc_vvssl_imm_2:
1278; CHECK:       # %bb.0:
1279; CHECK-NEXT:    lea %s1, 256
1280; CHECK-NEXT:    lvl %s1
1281; CHECK-NEXT:    vgtl.sx.nc %v0, %v0, 8, %s0
1282; CHECK-NEXT:    b.l.t (, %s10)
1283  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtlsxnc.vvssl(<256 x double> %0, i64 8, i64 %1, i32 256)
1284  ret <256 x double> %3
1285}
1286
1287; Function Attrs: nounwind readonly
1288define fastcc <256 x double> @vgtlsxnc_vvssvl_imm_2(<256 x double> %0, i64 %1, <256 x double> %2) {
1289; CHECK-LABEL: vgtlsxnc_vvssvl_imm_2:
1290; CHECK:       # %bb.0:
1291; CHECK-NEXT:    lea %s1, 128
1292; CHECK-NEXT:    lvl %s1
1293; CHECK-NEXT:    vgtl.sx.nc %v1, %v0, 8, %s0
1294; CHECK-NEXT:    lea %s16, 256
1295; CHECK-NEXT:    lvl %s16
1296; CHECK-NEXT:    vor %v0, (0)1, %v1
1297; CHECK-NEXT:    b.l.t (, %s10)
1298  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtlsxnc.vvssvl(<256 x double> %0, i64 8, i64 %1, <256 x double> %2, i32 128)
1299  ret <256 x double> %4
1300}
1301
1302; Function Attrs: nounwind readonly
1303define fastcc <256 x double> @vgtlsxnc_vvssl_imm_3(<256 x double> %0) {
1304; CHECK-LABEL: vgtlsxnc_vvssl_imm_3:
1305; CHECK:       # %bb.0:
1306; CHECK-NEXT:    lea %s0, 256
1307; CHECK-NEXT:    lvl %s0
1308; CHECK-NEXT:    vgtl.sx.nc %v0, %v0, 8, 0
1309; CHECK-NEXT:    b.l.t (, %s10)
1310  %2 = tail call fast <256 x double> @llvm.ve.vl.vgtlsxnc.vvssl(<256 x double> %0, i64 8, i64 0, i32 256)
1311  ret <256 x double> %2
1312}
1313
1314; Function Attrs: nounwind readonly
1315define fastcc <256 x double> @vgtlsxnc_vvssvl_imm_3(<256 x double> %0, <256 x double> %1) {
1316; CHECK-LABEL: vgtlsxnc_vvssvl_imm_3:
1317; CHECK:       # %bb.0:
1318; CHECK-NEXT:    lea %s0, 128
1319; CHECK-NEXT:    lvl %s0
1320; CHECK-NEXT:    vgtl.sx.nc %v1, %v0, 8, 0
1321; CHECK-NEXT:    lea %s16, 256
1322; CHECK-NEXT:    lvl %s16
1323; CHECK-NEXT:    vor %v0, (0)1, %v1
1324; CHECK-NEXT:    b.l.t (, %s10)
1325  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtlsxnc.vvssvl(<256 x double> %0, i64 8, i64 0, <256 x double> %1, i32 128)
1326  ret <256 x double> %3
1327}
1328
1329; Function Attrs: nounwind readonly
1330define fastcc <256 x double> @vgtlsxnc_vvssml(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3) {
1331; CHECK-LABEL: vgtlsxnc_vvssml:
1332; CHECK:       # %bb.0:
1333; CHECK-NEXT:    lea %s2, 256
1334; CHECK-NEXT:    lvl %s2
1335; CHECK-NEXT:    vgtl.sx.nc %v0, %v0, %s0, %s1, %vm1
1336; CHECK-NEXT:    b.l.t (, %s10)
1337  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtlsxnc.vvssml(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, i32 256)
1338  ret <256 x double> %5
1339}
1340
1341; Function Attrs: nounwind readonly
1342declare <256 x double> @llvm.ve.vl.vgtlsxnc.vvssml(<256 x double>, i64, i64, <256 x i1>, i32)
1343
1344; Function Attrs: nounwind readonly
1345define fastcc <256 x double> @vgtlsxnc_vvssmvl(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, <256 x double> %4) {
1346; CHECK-LABEL: vgtlsxnc_vvssmvl:
1347; CHECK:       # %bb.0:
1348; CHECK-NEXT:    lea %s2, 128
1349; CHECK-NEXT:    lvl %s2
1350; CHECK-NEXT:    vgtl.sx.nc %v1, %v0, %s0, %s1, %vm1
1351; CHECK-NEXT:    lea %s16, 256
1352; CHECK-NEXT:    lvl %s16
1353; CHECK-NEXT:    vor %v0, (0)1, %v1
1354; CHECK-NEXT:    b.l.t (, %s10)
1355  %6 = tail call fast <256 x double> @llvm.ve.vl.vgtlsxnc.vvssmvl(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, <256 x double> %4, i32 128)
1356  ret <256 x double> %6
1357}
1358
1359; Function Attrs: nounwind readonly
1360declare <256 x double> @llvm.ve.vl.vgtlsxnc.vvssmvl(<256 x double>, i64, i64, <256 x i1>, <256 x double>, i32)
1361
1362; Function Attrs: nounwind readonly
1363define fastcc <256 x double> @vgtlsxnc_vvssml_imm_1(<256 x double> %0, i64 %1, <256 x i1> %2) {
1364; CHECK-LABEL: vgtlsxnc_vvssml_imm_1:
1365; CHECK:       # %bb.0:
1366; CHECK-NEXT:    lea %s1, 256
1367; CHECK-NEXT:    lvl %s1
1368; CHECK-NEXT:    vgtl.sx.nc %v0, %v0, %s0, 0, %vm1
1369; CHECK-NEXT:    b.l.t (, %s10)
1370  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtlsxnc.vvssml(<256 x double> %0, i64 %1, i64 0, <256 x i1> %2, i32 256)
1371  ret <256 x double> %4
1372}
1373
1374; Function Attrs: nounwind readonly
1375define fastcc <256 x double> @vgtlsxnc_vvssmvl_imm_1(<256 x double> %0, i64 %1, <256 x i1> %2, <256 x double> %3) {
1376; CHECK-LABEL: vgtlsxnc_vvssmvl_imm_1:
1377; CHECK:       # %bb.0:
1378; CHECK-NEXT:    lea %s1, 128
1379; CHECK-NEXT:    lvl %s1
1380; CHECK-NEXT:    vgtl.sx.nc %v1, %v0, %s0, 0, %vm1
1381; CHECK-NEXT:    lea %s16, 256
1382; CHECK-NEXT:    lvl %s16
1383; CHECK-NEXT:    vor %v0, (0)1, %v1
1384; CHECK-NEXT:    b.l.t (, %s10)
1385  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtlsxnc.vvssmvl(<256 x double> %0, i64 %1, i64 0, <256 x i1> %2, <256 x double> %3, i32 128)
1386  ret <256 x double> %5
1387}
1388
1389; Function Attrs: nounwind readonly
1390define fastcc <256 x double> @vgtlsxnc_vvssml_imm_2(<256 x double> %0, i64 %1, <256 x i1> %2) {
1391; CHECK-LABEL: vgtlsxnc_vvssml_imm_2:
1392; CHECK:       # %bb.0:
1393; CHECK-NEXT:    lea %s1, 256
1394; CHECK-NEXT:    lvl %s1
1395; CHECK-NEXT:    vgtl.sx.nc %v0, %v0, 8, %s0, %vm1
1396; CHECK-NEXT:    b.l.t (, %s10)
1397  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtlsxnc.vvssml(<256 x double> %0, i64 8, i64 %1, <256 x i1> %2, i32 256)
1398  ret <256 x double> %4
1399}
1400
1401; Function Attrs: nounwind readonly
1402define fastcc <256 x double> @vgtlsxnc_vvssmvl_imm_2(<256 x double> %0, i64 %1, <256 x i1> %2, <256 x double> %3) {
1403; CHECK-LABEL: vgtlsxnc_vvssmvl_imm_2:
1404; CHECK:       # %bb.0:
1405; CHECK-NEXT:    lea %s1, 128
1406; CHECK-NEXT:    lvl %s1
1407; CHECK-NEXT:    vgtl.sx.nc %v1, %v0, 8, %s0, %vm1
1408; CHECK-NEXT:    lea %s16, 256
1409; CHECK-NEXT:    lvl %s16
1410; CHECK-NEXT:    vor %v0, (0)1, %v1
1411; CHECK-NEXT:    b.l.t (, %s10)
1412  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtlsxnc.vvssmvl(<256 x double> %0, i64 8, i64 %1, <256 x i1> %2, <256 x double> %3, i32 128)
1413  ret <256 x double> %5
1414}
1415
1416; Function Attrs: nounwind readonly
1417define fastcc <256 x double> @vgtlsxnc_vvssml_imm_3(<256 x double> %0, <256 x i1> %1) {
1418; CHECK-LABEL: vgtlsxnc_vvssml_imm_3:
1419; CHECK:       # %bb.0:
1420; CHECK-NEXT:    lea %s0, 256
1421; CHECK-NEXT:    lvl %s0
1422; CHECK-NEXT:    vgtl.sx.nc %v0, %v0, 8, 0, %vm1
1423; CHECK-NEXT:    b.l.t (, %s10)
1424  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtlsxnc.vvssml(<256 x double> %0, i64 8, i64 0, <256 x i1> %1, i32 256)
1425  ret <256 x double> %3
1426}
1427
1428; Function Attrs: nounwind readonly
1429define fastcc <256 x double> @vgtlsxnc_vvssmvl_imm_3(<256 x double> %0, <256 x i1> %1, <256 x double> %2) {
1430; CHECK-LABEL: vgtlsxnc_vvssmvl_imm_3:
1431; CHECK:       # %bb.0:
1432; CHECK-NEXT:    lea %s0, 128
1433; CHECK-NEXT:    lvl %s0
1434; CHECK-NEXT:    vgtl.sx.nc %v1, %v0, 8, 0, %vm1
1435; CHECK-NEXT:    lea %s16, 256
1436; CHECK-NEXT:    lvl %s16
1437; CHECK-NEXT:    vor %v0, (0)1, %v1
1438; CHECK-NEXT:    b.l.t (, %s10)
1439  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtlsxnc.vvssmvl(<256 x double> %0, i64 8, i64 0, <256 x i1> %1, <256 x double> %2, i32 128)
1440  ret <256 x double> %4
1441}
1442
1443; Function Attrs: nounwind readonly
1444define fastcc <256 x double> @vgtlsxnc_vvssl_no_imm_1(<256 x double> %0, i64 %1) {
1445; CHECK-LABEL: vgtlsxnc_vvssl_no_imm_1:
1446; CHECK:       # %bb.0:
1447; CHECK-NEXT:    lea %s1, 256
1448; CHECK-NEXT:    or %s2, 8, (0)1
1449; CHECK-NEXT:    lvl %s1
1450; CHECK-NEXT:    vgtl.sx.nc %v0, %v0, %s0, %s2
1451; CHECK-NEXT:    b.l.t (, %s10)
1452  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtlsxnc.vvssl(<256 x double> %0, i64 %1, i64 8, i32 256)
1453  ret <256 x double> %3
1454}
1455
1456; Function Attrs: nounwind readonly
1457define fastcc <256 x double> @vgtlzx_vvssl(<256 x double> %0, i64 %1, i64 %2) {
1458; CHECK-LABEL: vgtlzx_vvssl:
1459; CHECK:       # %bb.0:
1460; CHECK-NEXT:    lea %s2, 256
1461; CHECK-NEXT:    lvl %s2
1462; CHECK-NEXT:    vgtl.zx %v0, %v0, %s0, %s1
1463; CHECK-NEXT:    b.l.t (, %s10)
1464  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtlzx.vvssl(<256 x double> %0, i64 %1, i64 %2, i32 256)
1465  ret <256 x double> %4
1466}
1467
1468; Function Attrs: nounwind readonly
1469declare <256 x double> @llvm.ve.vl.vgtlzx.vvssl(<256 x double>, i64, i64, i32)
1470
1471; Function Attrs: nounwind readonly
1472define fastcc <256 x double> @vgtlzx_vvssvl(<256 x double> %0, i64 %1, i64 %2, <256 x double> %3) {
1473; CHECK-LABEL: vgtlzx_vvssvl:
1474; CHECK:       # %bb.0:
1475; CHECK-NEXT:    lea %s2, 128
1476; CHECK-NEXT:    lvl %s2
1477; CHECK-NEXT:    vgtl.zx %v1, %v0, %s0, %s1
1478; CHECK-NEXT:    lea %s16, 256
1479; CHECK-NEXT:    lvl %s16
1480; CHECK-NEXT:    vor %v0, (0)1, %v1
1481; CHECK-NEXT:    b.l.t (, %s10)
1482  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtlzx.vvssvl(<256 x double> %0, i64 %1, i64 %2, <256 x double> %3, i32 128)
1483  ret <256 x double> %5
1484}
1485
1486; Function Attrs: nounwind readonly
1487declare <256 x double> @llvm.ve.vl.vgtlzx.vvssvl(<256 x double>, i64, i64, <256 x double>, i32)
1488
1489; Function Attrs: nounwind readonly
1490define fastcc <256 x double> @vgtlzx_vvssl_imm_1(<256 x double> %0, i64 %1) {
1491; CHECK-LABEL: vgtlzx_vvssl_imm_1:
1492; CHECK:       # %bb.0:
1493; CHECK-NEXT:    lea %s1, 256
1494; CHECK-NEXT:    lvl %s1
1495; CHECK-NEXT:    vgtl.zx %v0, %v0, %s0, 0
1496; CHECK-NEXT:    b.l.t (, %s10)
1497  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtlzx.vvssl(<256 x double> %0, i64 %1, i64 0, i32 256)
1498  ret <256 x double> %3
1499}
1500
1501; Function Attrs: nounwind readonly
1502define fastcc <256 x double> @vgtlzx_vvssvl_imm_1(<256 x double> %0, i64 %1, <256 x double> %2) {
1503; CHECK-LABEL: vgtlzx_vvssvl_imm_1:
1504; CHECK:       # %bb.0:
1505; CHECK-NEXT:    lea %s1, 128
1506; CHECK-NEXT:    lvl %s1
1507; CHECK-NEXT:    vgtl.zx %v1, %v0, %s0, 0
1508; CHECK-NEXT:    lea %s16, 256
1509; CHECK-NEXT:    lvl %s16
1510; CHECK-NEXT:    vor %v0, (0)1, %v1
1511; CHECK-NEXT:    b.l.t (, %s10)
1512  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtlzx.vvssvl(<256 x double> %0, i64 %1, i64 0, <256 x double> %2, i32 128)
1513  ret <256 x double> %4
1514}
1515
1516; Function Attrs: nounwind readonly
1517define fastcc <256 x double> @vgtlzx_vvssl_imm_2(<256 x double> %0, i64 %1) {
1518; CHECK-LABEL: vgtlzx_vvssl_imm_2:
1519; CHECK:       # %bb.0:
1520; CHECK-NEXT:    lea %s1, 256
1521; CHECK-NEXT:    lvl %s1
1522; CHECK-NEXT:    vgtl.zx %v0, %v0, 8, %s0
1523; CHECK-NEXT:    b.l.t (, %s10)
1524  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtlzx.vvssl(<256 x double> %0, i64 8, i64 %1, i32 256)
1525  ret <256 x double> %3
1526}
1527
1528; Function Attrs: nounwind readonly
1529define fastcc <256 x double> @vgtlzx_vvssvl_imm_2(<256 x double> %0, i64 %1, <256 x double> %2) {
1530; CHECK-LABEL: vgtlzx_vvssvl_imm_2:
1531; CHECK:       # %bb.0:
1532; CHECK-NEXT:    lea %s1, 128
1533; CHECK-NEXT:    lvl %s1
1534; CHECK-NEXT:    vgtl.zx %v1, %v0, 8, %s0
1535; CHECK-NEXT:    lea %s16, 256
1536; CHECK-NEXT:    lvl %s16
1537; CHECK-NEXT:    vor %v0, (0)1, %v1
1538; CHECK-NEXT:    b.l.t (, %s10)
1539  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtlzx.vvssvl(<256 x double> %0, i64 8, i64 %1, <256 x double> %2, i32 128)
1540  ret <256 x double> %4
1541}
1542
1543; Function Attrs: nounwind readonly
1544define fastcc <256 x double> @vgtlzx_vvssl_imm_3(<256 x double> %0) {
1545; CHECK-LABEL: vgtlzx_vvssl_imm_3:
1546; CHECK:       # %bb.0:
1547; CHECK-NEXT:    lea %s0, 256
1548; CHECK-NEXT:    lvl %s0
1549; CHECK-NEXT:    vgtl.zx %v0, %v0, 8, 0
1550; CHECK-NEXT:    b.l.t (, %s10)
1551  %2 = tail call fast <256 x double> @llvm.ve.vl.vgtlzx.vvssl(<256 x double> %0, i64 8, i64 0, i32 256)
1552  ret <256 x double> %2
1553}
1554
1555; Function Attrs: nounwind readonly
1556define fastcc <256 x double> @vgtlzx_vvssvl_imm_3(<256 x double> %0, <256 x double> %1) {
1557; CHECK-LABEL: vgtlzx_vvssvl_imm_3:
1558; CHECK:       # %bb.0:
1559; CHECK-NEXT:    lea %s0, 128
1560; CHECK-NEXT:    lvl %s0
1561; CHECK-NEXT:    vgtl.zx %v1, %v0, 8, 0
1562; CHECK-NEXT:    lea %s16, 256
1563; CHECK-NEXT:    lvl %s16
1564; CHECK-NEXT:    vor %v0, (0)1, %v1
1565; CHECK-NEXT:    b.l.t (, %s10)
1566  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtlzx.vvssvl(<256 x double> %0, i64 8, i64 0, <256 x double> %1, i32 128)
1567  ret <256 x double> %3
1568}
1569
1570; Function Attrs: nounwind readonly
1571define fastcc <256 x double> @vgtlzx_vvssml(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3) {
1572; CHECK-LABEL: vgtlzx_vvssml:
1573; CHECK:       # %bb.0:
1574; CHECK-NEXT:    lea %s2, 256
1575; CHECK-NEXT:    lvl %s2
1576; CHECK-NEXT:    vgtl.zx %v0, %v0, %s0, %s1, %vm1
1577; CHECK-NEXT:    b.l.t (, %s10)
1578  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtlzx.vvssml(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, i32 256)
1579  ret <256 x double> %5
1580}
1581
1582; Function Attrs: nounwind readonly
1583declare <256 x double> @llvm.ve.vl.vgtlzx.vvssml(<256 x double>, i64, i64, <256 x i1>, i32)
1584
1585; Function Attrs: nounwind readonly
1586define fastcc <256 x double> @vgtlzx_vvssmvl(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, <256 x double> %4) {
1587; CHECK-LABEL: vgtlzx_vvssmvl:
1588; CHECK:       # %bb.0:
1589; CHECK-NEXT:    lea %s2, 128
1590; CHECK-NEXT:    lvl %s2
1591; CHECK-NEXT:    vgtl.zx %v1, %v0, %s0, %s1, %vm1
1592; CHECK-NEXT:    lea %s16, 256
1593; CHECK-NEXT:    lvl %s16
1594; CHECK-NEXT:    vor %v0, (0)1, %v1
1595; CHECK-NEXT:    b.l.t (, %s10)
1596  %6 = tail call fast <256 x double> @llvm.ve.vl.vgtlzx.vvssmvl(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, <256 x double> %4, i32 128)
1597  ret <256 x double> %6
1598}
1599
1600; Function Attrs: nounwind readonly
1601declare <256 x double> @llvm.ve.vl.vgtlzx.vvssmvl(<256 x double>, i64, i64, <256 x i1>, <256 x double>, i32)
1602
1603; Function Attrs: nounwind readonly
1604define fastcc <256 x double> @vgtlzx_vvssml_imm_1(<256 x double> %0, i64 %1, <256 x i1> %2) {
1605; CHECK-LABEL: vgtlzx_vvssml_imm_1:
1606; CHECK:       # %bb.0:
1607; CHECK-NEXT:    lea %s1, 256
1608; CHECK-NEXT:    lvl %s1
1609; CHECK-NEXT:    vgtl.zx %v0, %v0, %s0, 0, %vm1
1610; CHECK-NEXT:    b.l.t (, %s10)
1611  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtlzx.vvssml(<256 x double> %0, i64 %1, i64 0, <256 x i1> %2, i32 256)
1612  ret <256 x double> %4
1613}
1614
1615; Function Attrs: nounwind readonly
1616define fastcc <256 x double> @vgtlzx_vvssmvl_imm_1(<256 x double> %0, i64 %1, <256 x i1> %2, <256 x double> %3) {
1617; CHECK-LABEL: vgtlzx_vvssmvl_imm_1:
1618; CHECK:       # %bb.0:
1619; CHECK-NEXT:    lea %s1, 128
1620; CHECK-NEXT:    lvl %s1
1621; CHECK-NEXT:    vgtl.zx %v1, %v0, %s0, 0, %vm1
1622; CHECK-NEXT:    lea %s16, 256
1623; CHECK-NEXT:    lvl %s16
1624; CHECK-NEXT:    vor %v0, (0)1, %v1
1625; CHECK-NEXT:    b.l.t (, %s10)
1626  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtlzx.vvssmvl(<256 x double> %0, i64 %1, i64 0, <256 x i1> %2, <256 x double> %3, i32 128)
1627  ret <256 x double> %5
1628}
1629
1630; Function Attrs: nounwind readonly
1631define fastcc <256 x double> @vgtlzx_vvssml_imm_2(<256 x double> %0, i64 %1, <256 x i1> %2) {
1632; CHECK-LABEL: vgtlzx_vvssml_imm_2:
1633; CHECK:       # %bb.0:
1634; CHECK-NEXT:    lea %s1, 256
1635; CHECK-NEXT:    lvl %s1
1636; CHECK-NEXT:    vgtl.zx %v0, %v0, 8, %s0, %vm1
1637; CHECK-NEXT:    b.l.t (, %s10)
1638  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtlzx.vvssml(<256 x double> %0, i64 8, i64 %1, <256 x i1> %2, i32 256)
1639  ret <256 x double> %4
1640}
1641
1642; Function Attrs: nounwind readonly
1643define fastcc <256 x double> @vgtlzx_vvssmvl_imm_2(<256 x double> %0, i64 %1, <256 x i1> %2, <256 x double> %3) {
1644; CHECK-LABEL: vgtlzx_vvssmvl_imm_2:
1645; CHECK:       # %bb.0:
1646; CHECK-NEXT:    lea %s1, 128
1647; CHECK-NEXT:    lvl %s1
1648; CHECK-NEXT:    vgtl.zx %v1, %v0, 8, %s0, %vm1
1649; CHECK-NEXT:    lea %s16, 256
1650; CHECK-NEXT:    lvl %s16
1651; CHECK-NEXT:    vor %v0, (0)1, %v1
1652; CHECK-NEXT:    b.l.t (, %s10)
1653  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtlzx.vvssmvl(<256 x double> %0, i64 8, i64 %1, <256 x i1> %2, <256 x double> %3, i32 128)
1654  ret <256 x double> %5
1655}
1656
1657; Function Attrs: nounwind readonly
1658define fastcc <256 x double> @vgtlzx_vvssml_imm_3(<256 x double> %0, <256 x i1> %1) {
1659; CHECK-LABEL: vgtlzx_vvssml_imm_3:
1660; CHECK:       # %bb.0:
1661; CHECK-NEXT:    lea %s0, 256
1662; CHECK-NEXT:    lvl %s0
1663; CHECK-NEXT:    vgtl.zx %v0, %v0, 8, 0, %vm1
1664; CHECK-NEXT:    b.l.t (, %s10)
1665  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtlzx.vvssml(<256 x double> %0, i64 8, i64 0, <256 x i1> %1, i32 256)
1666  ret <256 x double> %3
1667}
1668
1669; Function Attrs: nounwind readonly
1670define fastcc <256 x double> @vgtlzx_vvssmvl_imm_3(<256 x double> %0, <256 x i1> %1, <256 x double> %2) {
1671; CHECK-LABEL: vgtlzx_vvssmvl_imm_3:
1672; CHECK:       # %bb.0:
1673; CHECK-NEXT:    lea %s0, 128
1674; CHECK-NEXT:    lvl %s0
1675; CHECK-NEXT:    vgtl.zx %v1, %v0, 8, 0, %vm1
1676; CHECK-NEXT:    lea %s16, 256
1677; CHECK-NEXT:    lvl %s16
1678; CHECK-NEXT:    vor %v0, (0)1, %v1
1679; CHECK-NEXT:    b.l.t (, %s10)
1680  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtlzx.vvssmvl(<256 x double> %0, i64 8, i64 0, <256 x i1> %1, <256 x double> %2, i32 128)
1681  ret <256 x double> %4
1682}
1683
1684; Function Attrs: nounwind readonly
1685define fastcc <256 x double> @vgtlzx_vvssl_no_imm_1(<256 x double> %0, i64 %1) {
1686; CHECK-LABEL: vgtlzx_vvssl_no_imm_1:
1687; CHECK:       # %bb.0:
1688; CHECK-NEXT:    lea %s1, 256
1689; CHECK-NEXT:    or %s2, 8, (0)1
1690; CHECK-NEXT:    lvl %s1
1691; CHECK-NEXT:    vgtl.zx %v0, %v0, %s0, %s2
1692; CHECK-NEXT:    b.l.t (, %s10)
1693  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtlzx.vvssl(<256 x double> %0, i64 %1, i64 8, i32 256)
1694  ret <256 x double> %3
1695}
1696
1697; Function Attrs: nounwind readonly
1698define fastcc <256 x double> @vgtlzxnc_vvssl(<256 x double> %0, i64 %1, i64 %2) {
1699; CHECK-LABEL: vgtlzxnc_vvssl:
1700; CHECK:       # %bb.0:
1701; CHECK-NEXT:    lea %s2, 256
1702; CHECK-NEXT:    lvl %s2
1703; CHECK-NEXT:    vgtl.zx.nc %v0, %v0, %s0, %s1
1704; CHECK-NEXT:    b.l.t (, %s10)
1705  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtlzxnc.vvssl(<256 x double> %0, i64 %1, i64 %2, i32 256)
1706  ret <256 x double> %4
1707}
1708
1709; Function Attrs: nounwind readonly
1710declare <256 x double> @llvm.ve.vl.vgtlzxnc.vvssl(<256 x double>, i64, i64, i32)
1711
1712; Function Attrs: nounwind readonly
1713define fastcc <256 x double> @vgtlzxnc_vvssvl(<256 x double> %0, i64 %1, i64 %2, <256 x double> %3) {
1714; CHECK-LABEL: vgtlzxnc_vvssvl:
1715; CHECK:       # %bb.0:
1716; CHECK-NEXT:    lea %s2, 128
1717; CHECK-NEXT:    lvl %s2
1718; CHECK-NEXT:    vgtl.zx.nc %v1, %v0, %s0, %s1
1719; CHECK-NEXT:    lea %s16, 256
1720; CHECK-NEXT:    lvl %s16
1721; CHECK-NEXT:    vor %v0, (0)1, %v1
1722; CHECK-NEXT:    b.l.t (, %s10)
1723  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtlzxnc.vvssvl(<256 x double> %0, i64 %1, i64 %2, <256 x double> %3, i32 128)
1724  ret <256 x double> %5
1725}
1726
1727; Function Attrs: nounwind readonly
1728declare <256 x double> @llvm.ve.vl.vgtlzxnc.vvssvl(<256 x double>, i64, i64, <256 x double>, i32)
1729
1730; Function Attrs: nounwind readonly
1731define fastcc <256 x double> @vgtlzxnc_vvssl_imm_1(<256 x double> %0, i64 %1) {
1732; CHECK-LABEL: vgtlzxnc_vvssl_imm_1:
1733; CHECK:       # %bb.0:
1734; CHECK-NEXT:    lea %s1, 256
1735; CHECK-NEXT:    lvl %s1
1736; CHECK-NEXT:    vgtl.zx.nc %v0, %v0, %s0, 0
1737; CHECK-NEXT:    b.l.t (, %s10)
1738  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtlzxnc.vvssl(<256 x double> %0, i64 %1, i64 0, i32 256)
1739  ret <256 x double> %3
1740}
1741
1742; Function Attrs: nounwind readonly
1743define fastcc <256 x double> @vgtlzxnc_vvssvl_imm_1(<256 x double> %0, i64 %1, <256 x double> %2) {
1744; CHECK-LABEL: vgtlzxnc_vvssvl_imm_1:
1745; CHECK:       # %bb.0:
1746; CHECK-NEXT:    lea %s1, 128
1747; CHECK-NEXT:    lvl %s1
1748; CHECK-NEXT:    vgtl.zx.nc %v1, %v0, %s0, 0
1749; CHECK-NEXT:    lea %s16, 256
1750; CHECK-NEXT:    lvl %s16
1751; CHECK-NEXT:    vor %v0, (0)1, %v1
1752; CHECK-NEXT:    b.l.t (, %s10)
1753  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtlzxnc.vvssvl(<256 x double> %0, i64 %1, i64 0, <256 x double> %2, i32 128)
1754  ret <256 x double> %4
1755}
1756
1757; Function Attrs: nounwind readonly
1758define fastcc <256 x double> @vgtlzxnc_vvssl_imm_2(<256 x double> %0, i64 %1) {
1759; CHECK-LABEL: vgtlzxnc_vvssl_imm_2:
1760; CHECK:       # %bb.0:
1761; CHECK-NEXT:    lea %s1, 256
1762; CHECK-NEXT:    lvl %s1
1763; CHECK-NEXT:    vgtl.zx.nc %v0, %v0, 8, %s0
1764; CHECK-NEXT:    b.l.t (, %s10)
1765  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtlzxnc.vvssl(<256 x double> %0, i64 8, i64 %1, i32 256)
1766  ret <256 x double> %3
1767}
1768
1769; Function Attrs: nounwind readonly
1770define fastcc <256 x double> @vgtlzxnc_vvssvl_imm_2(<256 x double> %0, i64 %1, <256 x double> %2) {
1771; CHECK-LABEL: vgtlzxnc_vvssvl_imm_2:
1772; CHECK:       # %bb.0:
1773; CHECK-NEXT:    lea %s1, 128
1774; CHECK-NEXT:    lvl %s1
1775; CHECK-NEXT:    vgtl.zx.nc %v1, %v0, 8, %s0
1776; CHECK-NEXT:    lea %s16, 256
1777; CHECK-NEXT:    lvl %s16
1778; CHECK-NEXT:    vor %v0, (0)1, %v1
1779; CHECK-NEXT:    b.l.t (, %s10)
1780  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtlzxnc.vvssvl(<256 x double> %0, i64 8, i64 %1, <256 x double> %2, i32 128)
1781  ret <256 x double> %4
1782}
1783
1784; Function Attrs: nounwind readonly
1785define fastcc <256 x double> @vgtlzxnc_vvssl_imm_3(<256 x double> %0) {
1786; CHECK-LABEL: vgtlzxnc_vvssl_imm_3:
1787; CHECK:       # %bb.0:
1788; CHECK-NEXT:    lea %s0, 256
1789; CHECK-NEXT:    lvl %s0
1790; CHECK-NEXT:    vgtl.zx.nc %v0, %v0, 8, 0
1791; CHECK-NEXT:    b.l.t (, %s10)
1792  %2 = tail call fast <256 x double> @llvm.ve.vl.vgtlzxnc.vvssl(<256 x double> %0, i64 8, i64 0, i32 256)
1793  ret <256 x double> %2
1794}
1795
1796; Function Attrs: nounwind readonly
1797define fastcc <256 x double> @vgtlzxnc_vvssvl_imm_3(<256 x double> %0, <256 x double> %1) {
1798; CHECK-LABEL: vgtlzxnc_vvssvl_imm_3:
1799; CHECK:       # %bb.0:
1800; CHECK-NEXT:    lea %s0, 128
1801; CHECK-NEXT:    lvl %s0
1802; CHECK-NEXT:    vgtl.zx.nc %v1, %v0, 8, 0
1803; CHECK-NEXT:    lea %s16, 256
1804; CHECK-NEXT:    lvl %s16
1805; CHECK-NEXT:    vor %v0, (0)1, %v1
1806; CHECK-NEXT:    b.l.t (, %s10)
1807  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtlzxnc.vvssvl(<256 x double> %0, i64 8, i64 0, <256 x double> %1, i32 128)
1808  ret <256 x double> %3
1809}
1810
1811; Function Attrs: nounwind readonly
1812define fastcc <256 x double> @vgtlzxnc_vvssml(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3) {
1813; CHECK-LABEL: vgtlzxnc_vvssml:
1814; CHECK:       # %bb.0:
1815; CHECK-NEXT:    lea %s2, 256
1816; CHECK-NEXT:    lvl %s2
1817; CHECK-NEXT:    vgtl.zx.nc %v0, %v0, %s0, %s1, %vm1
1818; CHECK-NEXT:    b.l.t (, %s10)
1819  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtlzxnc.vvssml(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, i32 256)
1820  ret <256 x double> %5
1821}
1822
1823; Function Attrs: nounwind readonly
1824declare <256 x double> @llvm.ve.vl.vgtlzxnc.vvssml(<256 x double>, i64, i64, <256 x i1>, i32)
1825
1826; Function Attrs: nounwind readonly
1827define fastcc <256 x double> @vgtlzxnc_vvssmvl(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, <256 x double> %4) {
1828; CHECK-LABEL: vgtlzxnc_vvssmvl:
1829; CHECK:       # %bb.0:
1830; CHECK-NEXT:    lea %s2, 128
1831; CHECK-NEXT:    lvl %s2
1832; CHECK-NEXT:    vgtl.zx.nc %v1, %v0, %s0, %s1, %vm1
1833; CHECK-NEXT:    lea %s16, 256
1834; CHECK-NEXT:    lvl %s16
1835; CHECK-NEXT:    vor %v0, (0)1, %v1
1836; CHECK-NEXT:    b.l.t (, %s10)
1837  %6 = tail call fast <256 x double> @llvm.ve.vl.vgtlzxnc.vvssmvl(<256 x double> %0, i64 %1, i64 %2, <256 x i1> %3, <256 x double> %4, i32 128)
1838  ret <256 x double> %6
1839}
1840
1841; Function Attrs: nounwind readonly
1842declare <256 x double> @llvm.ve.vl.vgtlzxnc.vvssmvl(<256 x double>, i64, i64, <256 x i1>, <256 x double>, i32)
1843
1844; Function Attrs: nounwind readonly
1845define fastcc <256 x double> @vgtlzxnc_vvssml_imm_1(<256 x double> %0, i64 %1, <256 x i1> %2) {
1846; CHECK-LABEL: vgtlzxnc_vvssml_imm_1:
1847; CHECK:       # %bb.0:
1848; CHECK-NEXT:    lea %s1, 256
1849; CHECK-NEXT:    lvl %s1
1850; CHECK-NEXT:    vgtl.zx.nc %v0, %v0, %s0, 0, %vm1
1851; CHECK-NEXT:    b.l.t (, %s10)
1852  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtlzxnc.vvssml(<256 x double> %0, i64 %1, i64 0, <256 x i1> %2, i32 256)
1853  ret <256 x double> %4
1854}
1855
1856; Function Attrs: nounwind readonly
1857define fastcc <256 x double> @vgtlzxnc_vvssmvl_imm_1(<256 x double> %0, i64 %1, <256 x i1> %2, <256 x double> %3) {
1858; CHECK-LABEL: vgtlzxnc_vvssmvl_imm_1:
1859; CHECK:       # %bb.0:
1860; CHECK-NEXT:    lea %s1, 128
1861; CHECK-NEXT:    lvl %s1
1862; CHECK-NEXT:    vgtl.zx.nc %v1, %v0, %s0, 0, %vm1
1863; CHECK-NEXT:    lea %s16, 256
1864; CHECK-NEXT:    lvl %s16
1865; CHECK-NEXT:    vor %v0, (0)1, %v1
1866; CHECK-NEXT:    b.l.t (, %s10)
1867  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtlzxnc.vvssmvl(<256 x double> %0, i64 %1, i64 0, <256 x i1> %2, <256 x double> %3, i32 128)
1868  ret <256 x double> %5
1869}
1870
1871; Function Attrs: nounwind readonly
1872define fastcc <256 x double> @vgtlzxnc_vvssml_imm_2(<256 x double> %0, i64 %1, <256 x i1> %2) {
1873; CHECK-LABEL: vgtlzxnc_vvssml_imm_2:
1874; CHECK:       # %bb.0:
1875; CHECK-NEXT:    lea %s1, 256
1876; CHECK-NEXT:    lvl %s1
1877; CHECK-NEXT:    vgtl.zx.nc %v0, %v0, 8, %s0, %vm1
1878; CHECK-NEXT:    b.l.t (, %s10)
1879  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtlzxnc.vvssml(<256 x double> %0, i64 8, i64 %1, <256 x i1> %2, i32 256)
1880  ret <256 x double> %4
1881}
1882
1883; Function Attrs: nounwind readonly
1884define fastcc <256 x double> @vgtlzxnc_vvssmvl_imm_2(<256 x double> %0, i64 %1, <256 x i1> %2, <256 x double> %3) {
1885; CHECK-LABEL: vgtlzxnc_vvssmvl_imm_2:
1886; CHECK:       # %bb.0:
1887; CHECK-NEXT:    lea %s1, 128
1888; CHECK-NEXT:    lvl %s1
1889; CHECK-NEXT:    vgtl.zx.nc %v1, %v0, 8, %s0, %vm1
1890; CHECK-NEXT:    lea %s16, 256
1891; CHECK-NEXT:    lvl %s16
1892; CHECK-NEXT:    vor %v0, (0)1, %v1
1893; CHECK-NEXT:    b.l.t (, %s10)
1894  %5 = tail call fast <256 x double> @llvm.ve.vl.vgtlzxnc.vvssmvl(<256 x double> %0, i64 8, i64 %1, <256 x i1> %2, <256 x double> %3, i32 128)
1895  ret <256 x double> %5
1896}
1897
1898; Function Attrs: nounwind readonly
1899define fastcc <256 x double> @vgtlzxnc_vvssml_imm_3(<256 x double> %0, <256 x i1> %1) {
1900; CHECK-LABEL: vgtlzxnc_vvssml_imm_3:
1901; CHECK:       # %bb.0:
1902; CHECK-NEXT:    lea %s0, 256
1903; CHECK-NEXT:    lvl %s0
1904; CHECK-NEXT:    vgtl.zx.nc %v0, %v0, 8, 0, %vm1
1905; CHECK-NEXT:    b.l.t (, %s10)
1906  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtlzxnc.vvssml(<256 x double> %0, i64 8, i64 0, <256 x i1> %1, i32 256)
1907  ret <256 x double> %3
1908}
1909
1910; Function Attrs: nounwind readonly
1911define fastcc <256 x double> @vgtlzxnc_vvssmvl_imm_3(<256 x double> %0, <256 x i1> %1, <256 x double> %2) {
1912; CHECK-LABEL: vgtlzxnc_vvssmvl_imm_3:
1913; CHECK:       # %bb.0:
1914; CHECK-NEXT:    lea %s0, 128
1915; CHECK-NEXT:    lvl %s0
1916; CHECK-NEXT:    vgtl.zx.nc %v1, %v0, 8, 0, %vm1
1917; CHECK-NEXT:    lea %s16, 256
1918; CHECK-NEXT:    lvl %s16
1919; CHECK-NEXT:    vor %v0, (0)1, %v1
1920; CHECK-NEXT:    b.l.t (, %s10)
1921  %4 = tail call fast <256 x double> @llvm.ve.vl.vgtlzxnc.vvssmvl(<256 x double> %0, i64 8, i64 0, <256 x i1> %1, <256 x double> %2, i32 128)
1922  ret <256 x double> %4
1923}
1924
1925; Function Attrs: nounwind readonly
1926define fastcc <256 x double> @vgtlzxnc_vvssl_no_imm_1(<256 x double> %0, i64 %1) {
1927; CHECK-LABEL: vgtlzxnc_vvssl_no_imm_1:
1928; CHECK:       # %bb.0:
1929; CHECK-NEXT:    lea %s1, 256
1930; CHECK-NEXT:    or %s2, 8, (0)1
1931; CHECK-NEXT:    lvl %s1
1932; CHECK-NEXT:    vgtl.zx.nc %v0, %v0, %s0, %s2
1933; CHECK-NEXT:    b.l.t (, %s10)
1934  %3 = tail call fast <256 x double> @llvm.ve.vl.vgtlzxnc.vvssl(<256 x double> %0, i64 %1, i64 8, i32 256)
1935  ret <256 x double> %3
1936}
1937