1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s 2 3;;; Test pack intrinsic instructions 4;;; 5;;; Note: 6;;; We test pack_f32p and pack_f32a pseudo instruction. 7 8; Function Attrs: nounwind readonly 9define fastcc i64 @pack_f32p(ptr readonly %0, ptr readonly %1) { 10; CHECK-LABEL: pack_f32p: 11; CHECK: # %bb.0: 12; CHECK-NEXT: ldu %s0, (, %s0) 13; CHECK-NEXT: ldl.zx %s1, (, %s1) 14; CHECK-NEXT: or %s0, %s0, %s1 15; CHECK-NEXT: b.l.t (, %s10) 16 %3 = tail call i64 @llvm.ve.vl.pack.f32p(ptr %0, ptr %1) 17 ret i64 %3 18} 19 20; Function Attrs: nounwind readonly 21declare i64 @llvm.ve.vl.pack.f32p(ptr, ptr) 22 23; Function Attrs: nounwind readonly 24define fastcc i64 @pack_f32a(ptr readonly %0) { 25; CHECK-LABEL: pack_f32a: 26; CHECK: # %bb.0: 27; CHECK-NEXT: ldl.zx %s0, (, %s0) 28; CHECK-NEXT: lea %s1, 1 29; CHECK-NEXT: and %s1, %s1, (32)0 30; CHECK-NEXT: lea.sl %s1, 1(, %s1) 31; CHECK-NEXT: mulu.l %s0, %s0, %s1 32; CHECK-NEXT: b.l.t (, %s10) 33 %2 = tail call i64 @llvm.ve.vl.pack.f32a(ptr %0) 34 ret i64 %2 35} 36 37; Function Attrs: nounwind readonly 38declare i64 @llvm.ve.vl.pack.f32a(ptr) 39