1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s 2 3;;; Test intrinsics for communication register 4;;; 5;;; Note: 6;;; We test LCR, SCR, TSCR, and FIDCR instructions. 7 8; Function Attrs: mustprogress nofree nosync nounwind readnone willreturn 9define i64 @lcr_sss(i64 noundef %0, i64 noundef %1) { 10; CHECK-LABEL: lcr_sss: 11; CHECK: # %bb.0: 12; CHECK-NEXT: lcr %s0, %s0, %s1 13; CHECK-NEXT: b.l.t (, %s10) 14 %3 = tail call i64 @llvm.ve.vl.lcr.sss(i64 %0, i64 %1) 15 ret i64 %3 16} 17 18; Function Attrs: nofree nosync nounwind readnone 19declare i64 @llvm.ve.vl.lcr.sss(i64, i64) 20 21; Function Attrs: nounwind 22define void @scr_sss(i64 noundef %0, i64 noundef %1, i64 noundef %2) { 23; CHECK-LABEL: scr_sss: 24; CHECK: # %bb.0: 25; CHECK-NEXT: scr %s0, %s1, %s2 26; CHECK-NEXT: b.l.t (, %s10) 27 tail call void @llvm.ve.vl.scr.sss(i64 %0, i64 %1, i64 %2) 28 ret void 29} 30 31; Function Attrs: nounwind 32declare void @llvm.ve.vl.scr.sss(i64, i64, i64) 33 34; Function Attrs: nounwind 35define i64 @tscr_ssss(i64 noundef %0, i64 noundef %1, i64 noundef %2) { 36; CHECK-LABEL: tscr_ssss: 37; CHECK: # %bb.0: 38; CHECK-NEXT: tscr %s0, %s1, %s2 39; CHECK-NEXT: b.l.t (, %s10) 40 %4 = tail call i64 @llvm.ve.vl.tscr.ssss(i64 %0, i64 %1, i64 %2) 41 ret i64 %4 42} 43 44; Function Attrs: nounwind 45declare i64 @llvm.ve.vl.tscr.ssss(i64, i64, i64) 46 47; Function Attrs: nounwind 48define i64 @fidcr_ss0(i64 noundef %0) { 49; CHECK-LABEL: fidcr_ss0: 50; CHECK: # %bb.0: 51; CHECK-NEXT: fidcr %s0, %s0, 0 52; CHECK-NEXT: b.l.t (, %s10) 53 %2 = tail call i64 @llvm.ve.vl.fidcr.sss(i64 %0, i32 0) 54 ret i64 %2 55} 56 57; Function Attrs: nounwind 58declare i64 @llvm.ve.vl.fidcr.sss(i64, i32) 59 60; Function Attrs: nounwind 61define i64 @fidcr_ss1(i64 noundef %0) { 62; CHECK-LABEL: fidcr_ss1: 63; CHECK: # %bb.0: 64; CHECK-NEXT: fidcr %s0, %s0, 1 65; CHECK-NEXT: b.l.t (, %s10) 66 %2 = tail call i64 @llvm.ve.vl.fidcr.sss(i64 %0, i32 1) 67 ret i64 %2 68} 69 70; Function Attrs: nounwind 71define i64 @fidcr_ss2(i64 noundef %0) { 72; CHECK-LABEL: fidcr_ss2: 73; CHECK: # %bb.0: 74; CHECK-NEXT: fidcr %s0, %s0, 2 75; CHECK-NEXT: b.l.t (, %s10) 76 %2 = tail call i64 @llvm.ve.vl.fidcr.sss(i64 %0, i32 2) 77 ret i64 %2 78} 79 80; Function Attrs: nounwind 81define i64 @fidcr_ss3(i64 noundef %0) { 82; CHECK-LABEL: fidcr_ss3: 83; CHECK: # %bb.0: 84; CHECK-NEXT: fidcr %s0, %s0, 3 85; CHECK-NEXT: b.l.t (, %s10) 86 %2 = tail call i64 @llvm.ve.vl.fidcr.sss(i64 %0, i32 3) 87 ret i64 %2 88} 89 90; Function Attrs: nounwind 91define i64 @fidcr_ss4(i64 noundef %0) { 92; CHECK-LABEL: fidcr_ss4: 93; CHECK: # %bb.0: 94; CHECK-NEXT: fidcr %s0, %s0, 4 95; CHECK-NEXT: b.l.t (, %s10) 96 %2 = tail call i64 @llvm.ve.vl.fidcr.sss(i64 %0, i32 4) 97 ret i64 %2 98} 99 100; Function Attrs: nounwind 101define i64 @fidcr_ss5(i64 noundef %0) { 102; CHECK-LABEL: fidcr_ss5: 103; CHECK: # %bb.0: 104; CHECK-NEXT: fidcr %s0, %s0, 5 105; CHECK-NEXT: b.l.t (, %s10) 106 %2 = tail call i64 @llvm.ve.vl.fidcr.sss(i64 %0, i32 5) 107 ret i64 %2 108} 109 110; Function Attrs: nounwind 111define i64 @fidcr_ss6(i64 noundef %0) { 112; CHECK-LABEL: fidcr_ss6: 113; CHECK: # %bb.0: 114; CHECK-NEXT: fidcr %s0, %s0, 6 115; CHECK-NEXT: b.l.t (, %s10) 116 %2 = tail call i64 @llvm.ve.vl.fidcr.sss(i64 %0, i32 6) 117 ret i64 %2 118} 119 120; Function Attrs: nounwind 121define i64 @fidcr_ss7(i64 noundef %0) { 122; CHECK-LABEL: fidcr_ss7: 123; CHECK: # %bb.0: 124; CHECK-NEXT: fidcr %s0, %s0, 7 125; CHECK-NEXT: b.l.t (, %s10) 126 %2 = tail call i64 @llvm.ve.vl.fidcr.sss(i64 %0, i32 7) 127 ret i64 %2 128} 129 130!2 = !{!"clang version 15.0.0 (git@kaz7.github.com:sx-aurora-dev/llvm-project.git e0c5640dba6e9ba1cd29ed8d59b85c6378e48ac7)"} 131