xref: /llvm-project/llvm/test/CodeGen/VE/Packed/vec_broadcast.ll (revision 5ceb0bc7eaccb318eb299ee308e01210a7da1d1e) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=ve-unknown-unknown -mattr=+vpu | FileCheck %s
3
4define fastcc <512 x i32> @brd_v512i32(i32 %s) {
5; CHECK-LABEL: brd_v512i32:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    and %s0, %s0, (32)0
8; CHECK-NEXT:    sll %s1, %s0, 32
9; CHECK-NEXT:    and %s0, %s0, (32)0
10; CHECK-NEXT:    or %s0, %s0, %s1
11; CHECK-NEXT:    lea %s1, 256
12; CHECK-NEXT:    lvl %s1
13; CHECK-NEXT:    vbrd %v0, %s0
14; CHECK-NEXT:    b.l.t (, %s10)
15  %val = insertelement <512 x i32> undef, i32 %s, i32 0
16  %ret = shufflevector <512 x i32> %val, <512 x i32> undef, <512 x i32> zeroinitializer
17  ret <512 x i32> %ret
18}
19
20define fastcc <512 x i32> @brdi_v512i32() {
21; CHECK-LABEL: brdi_v512i32:
22; CHECK:       # %bb.0:
23; CHECK-NEXT:    or %s0, 17, (0)1
24; CHECK-NEXT:    sll %s1, %s0, 32
25; CHECK-NEXT:    and %s0, %s0, (32)0
26; CHECK-NEXT:    or %s0, %s0, %s1
27; CHECK-NEXT:    lea %s1, 256
28; CHECK-NEXT:    lvl %s1
29; CHECK-NEXT:    vbrd %v0, %s0
30; CHECK-NEXT:    b.l.t (, %s10)
31  %val = insertelement <512 x i32> undef, i32 17, i32 0
32  %ret = shufflevector <512 x i32> %val, <512 x i32> undef, <512 x i32> zeroinitializer
33  ret <512 x i32> %ret
34}
35
36define fastcc <512 x float> @brd_v512f32(float %s) {
37; CHECK-LABEL: brd_v512f32:
38; CHECK:       # %bb.0:
39; CHECK-NEXT:    and %s1, %s0, (32)1
40; CHECK-NEXT:    srl %s0, %s0, 32
41; CHECK-NEXT:    or %s0, %s0, %s1
42; CHECK-NEXT:    lea %s1, 256
43; CHECK-NEXT:    lvl %s1
44; CHECK-NEXT:    vbrd %v0, %s0
45; CHECK-NEXT:    b.l.t (, %s10)
46  %val = insertelement <512 x float> undef, float %s, i32 0
47  %ret = shufflevector <512 x float> %val, <512 x float> undef, <512 x i32> zeroinitializer
48  ret <512 x float> %ret
49}
50
51define fastcc <512 x float> @brdi_v512f32() {
52; CHECK-LABEL: brdi_v512f32:
53; CHECK:       # %bb.0:
54; CHECK-NEXT:    lea.sl %s0, 0
55; CHECK-NEXT:    and %s1, %s0, (32)1
56; CHECK-NEXT:    srl %s0, %s0, 32
57; CHECK-NEXT:    or %s0, %s0, %s1
58; CHECK-NEXT:    lea %s1, 256
59; CHECK-NEXT:    lvl %s1
60; CHECK-NEXT:    vbrd %v0, %s0
61; CHECK-NEXT:    b.l.t (, %s10)
62  %val = insertelement <512 x float> undef, float 0.e+00, i32 0
63  %ret = shufflevector <512 x float> %val, <512 x float> undef, <512 x i32> zeroinitializer
64  ret <512 x float> %ret
65}
66