1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s 3 4define arm_aapcs_vfpcc void @vstrw32() { 5; CHECK-LABEL: vstrw32: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: .save {r7, lr} 8; CHECK-NEXT: push {r7, lr} 9; CHECK-NEXT: .pad #16 10; CHECK-NEXT: sub sp, #16 11; CHECK-NEXT: vmov.i32 q0, #0x0 12; CHECK-NEXT: mov r0, sp 13; CHECK-NEXT: vstrw.32 q0, [sp, #8] 14; CHECK-NEXT: bl func 15; CHECK-NEXT: add sp, #16 16; CHECK-NEXT: pop {r7, pc} 17entry: 18 %d = alloca [4 x i32], align 4 19 %g = getelementptr inbounds [4 x i32], ptr %d, i32 0, i32 2 20 store <4 x i32> zeroinitializer, ptr %g, align 2 21 call arm_aapcs_vfpcc void @func(ptr %d) 22 ret void 23} 24 25define arm_aapcs_vfpcc void @vstrh16() { 26; CHECK-LABEL: vstrh16: 27; CHECK: @ %bb.0: @ %entry 28; CHECK-NEXT: .save {r7, lr} 29; CHECK-NEXT: push {r7, lr} 30; CHECK-NEXT: .pad #16 31; CHECK-NEXT: sub sp, #16 32; CHECK-NEXT: vmov.i32 q0, #0x0 33; CHECK-NEXT: mov r0, sp 34; CHECK-NEXT: vstrh.16 q0, [sp, #4] 35; CHECK-NEXT: bl func 36; CHECK-NEXT: add sp, #16 37; CHECK-NEXT: pop {r7, pc} 38entry: 39 %d = alloca [8 x i16], align 2 40 %g = getelementptr inbounds [8 x i16], ptr %d, i32 0, i32 2 41 store <8 x i16> zeroinitializer, ptr %g, align 2 42 call arm_aapcs_vfpcc void @func(ptr %d) 43 ret void 44} 45 46define arm_aapcs_vfpcc void @vstrb8() { 47; CHECK-LABEL: vstrb8: 48; CHECK: @ %bb.0: @ %entry 49; CHECK-NEXT: .save {r7, lr} 50; CHECK-NEXT: push {r7, lr} 51; CHECK-NEXT: .pad #16 52; CHECK-NEXT: sub sp, #16 53; CHECK-NEXT: vmov.i32 q0, #0x0 54; CHECK-NEXT: mov r0, sp 55; CHECK-NEXT: vstrh.16 q0, [sp, #2] 56; CHECK-NEXT: bl func 57; CHECK-NEXT: add sp, #16 58; CHECK-NEXT: pop {r7, pc} 59entry: 60 %d = alloca [16 x i8], align 4 61 %g = getelementptr inbounds [16 x i8], ptr %d, i32 0, i32 2 62 store <16 x i8> zeroinitializer, ptr %g, align 2 63 call arm_aapcs_vfpcc void @func(ptr %d) 64 ret void 65} 66 67define arm_aapcs_vfpcc void @vstrh32() { 68; CHECK-LABEL: vstrh32: 69; CHECK: @ %bb.0: @ %entry 70; CHECK-NEXT: .save {r7, lr} 71; CHECK-NEXT: push {r7, lr} 72; CHECK-NEXT: .pad #8 73; CHECK-NEXT: sub sp, #8 74; CHECK-NEXT: mov r0, sp 75; CHECK-NEXT: vmov.i32 q0, #0x6 76; CHECK-NEXT: vstrh.32 q0, [r0, #4] 77; CHECK-NEXT: bl func 78; CHECK-NEXT: add sp, #8 79; CHECK-NEXT: pop {r7, pc} 80entry: 81 %d = alloca [4 x i16], align 4 82 %g = getelementptr inbounds [4 x i16], ptr %d, i32 0, i32 2 83 store <4 x i16> <i16 6, i16 6, i16 6, i16 6>, ptr %g, align 2 84 call arm_aapcs_vfpcc void @func(ptr %d) 85 ret void 86} 87 88define arm_aapcs_vfpcc void @vstrb32() { 89; CHECK-LABEL: vstrb32: 90; CHECK: @ %bb.0: @ %entry 91; CHECK-NEXT: .save {r7, lr} 92; CHECK-NEXT: push {r7, lr} 93; CHECK-NEXT: .pad #8 94; CHECK-NEXT: sub sp, #8 95; CHECK-NEXT: add r0, sp, #4 96; CHECK-NEXT: vmov.i32 q0, #0x6 97; CHECK-NEXT: vstrb.32 q0, [r0, #2] 98; CHECK-NEXT: bl func 99; CHECK-NEXT: add sp, #8 100; CHECK-NEXT: pop {r7, pc} 101entry: 102 %d = alloca [4 x i8], align 4 103 %g = getelementptr inbounds [4 x i8], ptr %d, i32 0, i32 2 104 store <4 x i8> <i8 6, i8 6, i8 6, i8 6>, ptr %g, align 2 105 call arm_aapcs_vfpcc void @func(ptr %d) 106 ret void 107} 108 109define arm_aapcs_vfpcc void @vstrb16() { 110; CHECK-LABEL: vstrb16: 111; CHECK: @ %bb.0: @ %entry 112; CHECK-NEXT: .save {r7, lr} 113; CHECK-NEXT: push {r7, lr} 114; CHECK-NEXT: .pad #8 115; CHECK-NEXT: sub sp, #8 116; CHECK-NEXT: mov r0, sp 117; CHECK-NEXT: vmov.i32 q0, #0x0 118; CHECK-NEXT: vstrb.16 q0, [r0, #2] 119; CHECK-NEXT: bl func 120; CHECK-NEXT: add sp, #8 121; CHECK-NEXT: pop {r7, pc} 122entry: 123 %d = alloca [8 x i8], align 4 124 %g = getelementptr inbounds [8 x i8], ptr %d, i32 0, i32 2 125 store <8 x i8> zeroinitializer, ptr %g, align 2 126 call arm_aapcs_vfpcc void @func(ptr %d) 127 ret void 128} 129 130 131define arm_aapcs_vfpcc <4 x i32> @vldrw32() { 132; CHECK-LABEL: vldrw32: 133; CHECK: @ %bb.0: @ %entry 134; CHECK-NEXT: .save {r7, lr} 135; CHECK-NEXT: push {r7, lr} 136; CHECK-NEXT: .pad #16 137; CHECK-NEXT: sub sp, #16 138; CHECK-NEXT: mov r0, sp 139; CHECK-NEXT: bl func 140; CHECK-NEXT: vldrw.u32 q0, [sp, #8] 141; CHECK-NEXT: add sp, #16 142; CHECK-NEXT: pop {r7, pc} 143entry: 144 %d = alloca [4 x i32], align 4 145 call arm_aapcs_vfpcc void @func(ptr %d) 146 %g = getelementptr inbounds [4 x i32], ptr %d, i32 0, i32 2 147 %l = load <4 x i32>, ptr %g, align 2 148 ret <4 x i32> %l 149} 150 151define arm_aapcs_vfpcc <8 x i16> @vldrh16() { 152; CHECK-LABEL: vldrh16: 153; CHECK: @ %bb.0: @ %entry 154; CHECK-NEXT: .save {r7, lr} 155; CHECK-NEXT: push {r7, lr} 156; CHECK-NEXT: .pad #16 157; CHECK-NEXT: sub sp, #16 158; CHECK-NEXT: mov r0, sp 159; CHECK-NEXT: bl func 160; CHECK-NEXT: vldrh.u16 q0, [sp, #4] 161; CHECK-NEXT: add sp, #16 162; CHECK-NEXT: pop {r7, pc} 163entry: 164 %d = alloca [8 x i16], align 2 165 call arm_aapcs_vfpcc void @func(ptr %d) 166 %g = getelementptr inbounds [8 x i16], ptr %d, i32 0, i32 2 167 %l = load <8 x i16>, ptr %g, align 2 168 ret <8 x i16> %l 169} 170 171define arm_aapcs_vfpcc <16 x i8> @vldrb8() { 172; CHECK-LABEL: vldrb8: 173; CHECK: @ %bb.0: @ %entry 174; CHECK-NEXT: .save {r7, lr} 175; CHECK-NEXT: push {r7, lr} 176; CHECK-NEXT: .pad #16 177; CHECK-NEXT: sub sp, #16 178; CHECK-NEXT: mov r0, sp 179; CHECK-NEXT: bl func 180; CHECK-NEXT: vldrh.u16 q0, [sp, #2] 181; CHECK-NEXT: add sp, #16 182; CHECK-NEXT: pop {r7, pc} 183entry: 184 %d = alloca [16 x i8], align 4 185 call arm_aapcs_vfpcc void @func(ptr %d) 186 %g = getelementptr inbounds [16 x i8], ptr %d, i32 0, i32 2 187 %l = load <16 x i8>, ptr %g, align 2 188 ret <16 x i8> %l 189} 190 191define arm_aapcs_vfpcc <4 x i16> @vldrh32() { 192; CHECK-LABEL: vldrh32: 193; CHECK: @ %bb.0: @ %entry 194; CHECK-NEXT: .save {r4, lr} 195; CHECK-NEXT: push {r4, lr} 196; CHECK-NEXT: .pad #8 197; CHECK-NEXT: sub sp, #8 198; CHECK-NEXT: mov r4, sp 199; CHECK-NEXT: mov r0, r4 200; CHECK-NEXT: bl func 201; CHECK-NEXT: vldrh.u32 q0, [r4, #4] 202; CHECK-NEXT: add sp, #8 203; CHECK-NEXT: pop {r4, pc} 204entry: 205 %d = alloca [4 x i16], align 4 206 call arm_aapcs_vfpcc void @func(ptr %d) 207 %g = getelementptr inbounds [4 x i16], ptr %d, i32 0, i32 2 208 %l = load <4 x i16>, ptr %g, align 2 209 ret <4 x i16> %l 210} 211 212define arm_aapcs_vfpcc <4 x i8> @vldrb32() { 213; CHECK-LABEL: vldrb32: 214; CHECK: @ %bb.0: @ %entry 215; CHECK-NEXT: .save {r4, lr} 216; CHECK-NEXT: push {r4, lr} 217; CHECK-NEXT: .pad #8 218; CHECK-NEXT: sub sp, #8 219; CHECK-NEXT: add r4, sp, #4 220; CHECK-NEXT: mov r0, r4 221; CHECK-NEXT: bl func 222; CHECK-NEXT: vldrb.u32 q0, [r4, #2] 223; CHECK-NEXT: add sp, #8 224; CHECK-NEXT: pop {r4, pc} 225entry: 226 %d = alloca [4 x i8], align 4 227 call arm_aapcs_vfpcc void @func(ptr %d) 228 %g = getelementptr inbounds [4 x i8], ptr %d, i32 0, i32 2 229 %l = load <4 x i8>, ptr %g, align 2 230 ret <4 x i8> %l 231} 232 233define arm_aapcs_vfpcc <8 x i8> @vldrb16() { 234; CHECK-LABEL: vldrb16: 235; CHECK: @ %bb.0: @ %entry 236; CHECK-NEXT: .save {r4, lr} 237; CHECK-NEXT: push {r4, lr} 238; CHECK-NEXT: .pad #8 239; CHECK-NEXT: sub sp, #8 240; CHECK-NEXT: mov r4, sp 241; CHECK-NEXT: mov r0, r4 242; CHECK-NEXT: bl func 243; CHECK-NEXT: vldrb.u16 q0, [r4, #2] 244; CHECK-NEXT: add sp, #8 245; CHECK-NEXT: pop {r4, pc} 246entry: 247 %d = alloca [8 x i8], align 4 248 call arm_aapcs_vfpcc void @func(ptr %d) 249 %g = getelementptr inbounds [8 x i8], ptr %d, i32 0, i32 2 250 %l = load <8 x i8>, ptr %g, align 2 251 ret <8 x i8> %l 252} 253 254declare dso_local arm_aapcs_vfpcc void @func(...) 255