xref: /llvm-project/llvm/test/CodeGen/Thumb2/mve-pred-ext.ll (revision e0ed0333f0fed2e73f805afd58b61176a87aa3ad) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-MVE
3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-MVEFP
4
5define arm_aapcs_vfpcc <4 x i32> @sext_v4i1_v4i32(<4 x i32> %src) {
6; CHECK-LABEL: sext_v4i1_v4i32:
7; CHECK:       @ %bb.0: @ %entry
8; CHECK-NEXT:    vmov.i32 q1, #0x0
9; CHECK-NEXT:    vmov.i8 q2, #0xff
10; CHECK-NEXT:    vcmp.s32 gt, q0, zr
11; CHECK-NEXT:    vpsel q0, q2, q1
12; CHECK-NEXT:    bx lr
13entry:
14  %c = icmp sgt <4 x i32> %src, zeroinitializer
15  %0 = sext <4 x i1> %c to <4 x i32>
16  ret <4 x i32> %0
17}
18
19define arm_aapcs_vfpcc <4 x i32> @sext_v4i1_v4f32(<4 x float> %src1, <4 x float> %src2) {
20; CHECK-MVE-LABEL: sext_v4i1_v4f32:
21; CHECK-MVE:       @ %bb.0: @ %entry
22; CHECK-MVE-NEXT:    vcmp.f32 s2, s6
23; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
24; CHECK-MVE-NEXT:    vcmp.f32 s0, s4
25; CHECK-MVE-NEXT:    csetm r0, ne
26; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
27; CHECK-MVE-NEXT:    vcmp.f32 s3, s7
28; CHECK-MVE-NEXT:    csetm r1, ne
29; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
30; CHECK-MVE-NEXT:    vcmp.f32 s1, s5
31; CHECK-MVE-NEXT:    vmov q2[2], q2[0], r1, r0
32; CHECK-MVE-NEXT:    csetm r0, ne
33; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
34; CHECK-MVE-NEXT:    csetm r1, ne
35; CHECK-MVE-NEXT:    vmov q2[3], q2[1], r1, r0
36; CHECK-MVE-NEXT:    vmov q0, q2
37; CHECK-MVE-NEXT:    bx lr
38;
39; CHECK-MVEFP-LABEL: sext_v4i1_v4f32:
40; CHECK-MVEFP:       @ %bb.0: @ %entry
41; CHECK-MVEFP-NEXT:    vmov.i32 q2, #0x0
42; CHECK-MVEFP-NEXT:    vmov.i8 q3, #0xff
43; CHECK-MVEFP-NEXT:    vcmp.f32 ne, q0, q1
44; CHECK-MVEFP-NEXT:    vpsel q0, q3, q2
45; CHECK-MVEFP-NEXT:    bx lr
46entry:
47  %c = fcmp une <4 x float> %src1, %src2
48  %0 = sext <4 x i1> %c to <4 x i32>
49  ret <4 x i32> %0
50}
51
52define arm_aapcs_vfpcc <8 x i16> @sext_v8i1_v8i16(<8 x i16> %src) {
53; CHECK-LABEL: sext_v8i1_v8i16:
54; CHECK:       @ %bb.0: @ %entry
55; CHECK-NEXT:    vmov.i16 q1, #0x0
56; CHECK-NEXT:    vmov.i8 q2, #0xff
57; CHECK-NEXT:    vcmp.s16 gt, q0, zr
58; CHECK-NEXT:    vpsel q0, q2, q1
59; CHECK-NEXT:    bx lr
60entry:
61  %c = icmp sgt <8 x i16> %src, zeroinitializer
62  %0 = sext <8 x i1> %c to <8 x i16>
63  ret <8 x i16> %0
64}
65
66define arm_aapcs_vfpcc <8 x i16> @sext_v8i1_v8f32(<8 x half> %src1, <8 x half> %src2) {
67; CHECK-MVE-LABEL: sext_v8i1_v8f32:
68; CHECK-MVE:       @ %bb.0: @ %entry
69; CHECK-MVE-NEXT:    .save {r4, lr}
70; CHECK-MVE-NEXT:    push {r4, lr}
71; CHECK-MVE-NEXT:    vcmp.f16 s3, s7
72; CHECK-MVE-NEXT:    vmovx.f16 s8, s6
73; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
74; CHECK-MVE-NEXT:    vmovx.f16 s10, s2
75; CHECK-MVE-NEXT:    vcmp.f16 s10, s8
76; CHECK-MVE-NEXT:    vmovx.f16 s8, s5
77; CHECK-MVE-NEXT:    vmovx.f16 s10, s1
78; CHECK-MVE-NEXT:    csetm r12, ne
79; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
80; CHECK-MVE-NEXT:    vcmp.f16 s10, s8
81; CHECK-MVE-NEXT:    csetm lr, ne
82; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
83; CHECK-MVE-NEXT:    vcmp.f16 s2, s6
84; CHECK-MVE-NEXT:    vmovx.f16 s2, s4
85; CHECK-MVE-NEXT:    vmovx.f16 s6, s0
86; CHECK-MVE-NEXT:    csetm r2, ne
87; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
88; CHECK-MVE-NEXT:    vcmp.f16 s6, s2
89; CHECK-MVE-NEXT:    vmovx.f16 s2, s3
90; CHECK-MVE-NEXT:    csetm r3, ne
91; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
92; CHECK-MVE-NEXT:    vcmp.f16 s1, s5
93; CHECK-MVE-NEXT:    csetm r0, ne
94; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
95; CHECK-MVE-NEXT:    vcmp.f16 s0, s4
96; CHECK-MVE-NEXT:    vmovx.f16 s0, s7
97; CHECK-MVE-NEXT:    csetm r1, ne
98; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
99; CHECK-MVE-NEXT:    vcmp.f16 s2, s0
100; CHECK-MVE-NEXT:    csetm r4, ne
101; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
102; CHECK-MVE-NEXT:    vmov.16 q0[0], r4
103; CHECK-MVE-NEXT:    vmov.16 q0[1], r0
104; CHECK-MVE-NEXT:    vmov.16 q0[2], r1
105; CHECK-MVE-NEXT:    vmov.16 q0[3], r2
106; CHECK-MVE-NEXT:    vmov.16 q0[4], r3
107; CHECK-MVE-NEXT:    vmov.16 q0[5], lr
108; CHECK-MVE-NEXT:    vmov.16 q0[6], r12
109; CHECK-MVE-NEXT:    csetm r0, ne
110; CHECK-MVE-NEXT:    vmov.16 q0[7], r0
111; CHECK-MVE-NEXT:    pop {r4, pc}
112;
113; CHECK-MVEFP-LABEL: sext_v8i1_v8f32:
114; CHECK-MVEFP:       @ %bb.0: @ %entry
115; CHECK-MVEFP-NEXT:    vmov.i16 q2, #0x0
116; CHECK-MVEFP-NEXT:    vmov.i8 q3, #0xff
117; CHECK-MVEFP-NEXT:    vcmp.f16 ne, q0, q1
118; CHECK-MVEFP-NEXT:    vpsel q0, q3, q2
119; CHECK-MVEFP-NEXT:    bx lr
120entry:
121  %c = fcmp une <8 x half> %src1, %src2
122  %0 = sext <8 x i1> %c to <8 x i16>
123  ret <8 x i16> %0
124}
125
126define arm_aapcs_vfpcc <16 x i8> @sext_v16i1_v16i8(<16 x i8> %src) {
127; CHECK-LABEL: sext_v16i1_v16i8:
128; CHECK:       @ %bb.0: @ %entry
129; CHECK-NEXT:    vmov.i8 q1, #0x0
130; CHECK-NEXT:    vmov.i8 q2, #0xff
131; CHECK-NEXT:    vcmp.s8 gt, q0, zr
132; CHECK-NEXT:    vpsel q0, q2, q1
133; CHECK-NEXT:    bx lr
134entry:
135  %c = icmp sgt <16 x i8> %src, zeroinitializer
136  %0 = sext <16 x i1> %c to <16 x i8>
137  ret <16 x i8> %0
138}
139
140define arm_aapcs_vfpcc <2 x i64> @sext_v2i1_v2i64(<2 x i64> %src) {
141; CHECK-LABEL: sext_v2i1_v2i64:
142; CHECK:       @ %bb.0: @ %entry
143; CHECK-NEXT:    vmov r0, r1, d1
144; CHECK-NEXT:    mov.w r12, #0
145; CHECK-NEXT:    vmov r2, r3, d0
146; CHECK-NEXT:    rsbs r0, r0, #0
147; CHECK-NEXT:    sbcs.w r0, r12, r1
148; CHECK-NEXT:    csetm r0, lt
149; CHECK-NEXT:    rsbs r1, r2, #0
150; CHECK-NEXT:    sbcs.w r1, r12, r3
151; CHECK-NEXT:    csetm r1, lt
152; CHECK-NEXT:    vmov q0[2], q0[0], r1, r0
153; CHECK-NEXT:    vmov q0[3], q0[1], r1, r0
154; CHECK-NEXT:    bx lr
155entry:
156  %c = icmp sgt <2 x i64> %src, zeroinitializer
157  %0 = sext <2 x i1> %c to <2 x i64>
158  ret <2 x i64> %0
159}
160
161define arm_aapcs_vfpcc <2 x i64> @sext_v2i1_v2f64(<2 x double> %src) {
162; CHECK-MVE-LABEL: sext_v2i1_v2f64:
163; CHECK-MVE:       @ %bb.0: @ %entry
164; CHECK-MVE-NEXT:    .save {r4, r5, r6, lr}
165; CHECK-MVE-NEXT:    push {r4, r5, r6, lr}
166; CHECK-MVE-NEXT:    .vsave {d8, d9}
167; CHECK-MVE-NEXT:    vpush {d8, d9}
168; CHECK-MVE-NEXT:    vmov q4, q0
169; CHECK-MVE-NEXT:    vldr d0, .LCPI6_0
170; CHECK-MVE-NEXT:    vmov r0, r1, d9
171; CHECK-MVE-NEXT:    vmov r4, r5, d0
172; CHECK-MVE-NEXT:    mov r2, r4
173; CHECK-MVE-NEXT:    mov r3, r5
174; CHECK-MVE-NEXT:    bl __aeabi_dcmpeq
175; CHECK-MVE-NEXT:    vmov r2, r1, d8
176; CHECK-MVE-NEXT:    cmp r0, #0
177; CHECK-MVE-NEXT:    mov r3, r5
178; CHECK-MVE-NEXT:    csetm r6, eq
179; CHECK-MVE-NEXT:    mov r0, r2
180; CHECK-MVE-NEXT:    mov r2, r4
181; CHECK-MVE-NEXT:    bl __aeabi_dcmpeq
182; CHECK-MVE-NEXT:    cmp r0, #0
183; CHECK-MVE-NEXT:    csetm r0, eq
184; CHECK-MVE-NEXT:    vmov q0[2], q0[0], r0, r6
185; CHECK-MVE-NEXT:    vmov q0[3], q0[1], r0, r6
186; CHECK-MVE-NEXT:    vpop {d8, d9}
187; CHECK-MVE-NEXT:    pop {r4, r5, r6, pc}
188; CHECK-MVE-NEXT:    .p2align 3
189; CHECK-MVE-NEXT:  @ %bb.1:
190; CHECK-MVE-NEXT:  .LCPI6_0:
191; CHECK-MVE-NEXT:    .long 0 @ double 0
192; CHECK-MVE-NEXT:    .long 0
193;
194; CHECK-MVEFP-LABEL: sext_v2i1_v2f64:
195; CHECK-MVEFP:       @ %bb.0: @ %entry
196; CHECK-MVEFP-NEXT:    .save {r4, r5, r6, lr}
197; CHECK-MVEFP-NEXT:    push {r4, r5, r6, lr}
198; CHECK-MVEFP-NEXT:    .vsave {d8, d9}
199; CHECK-MVEFP-NEXT:    vpush {d8, d9}
200; CHECK-MVEFP-NEXT:    vmov q4, q0
201; CHECK-MVEFP-NEXT:    vldr d0, .LCPI6_0
202; CHECK-MVEFP-NEXT:    vmov r0, r1, d8
203; CHECK-MVEFP-NEXT:    vmov r4, r5, d0
204; CHECK-MVEFP-NEXT:    mov r2, r4
205; CHECK-MVEFP-NEXT:    mov r3, r5
206; CHECK-MVEFP-NEXT:    bl __aeabi_dcmpeq
207; CHECK-MVEFP-NEXT:    mov r6, r0
208; CHECK-MVEFP-NEXT:    vmov r0, r1, d9
209; CHECK-MVEFP-NEXT:    mov r2, r4
210; CHECK-MVEFP-NEXT:    mov r3, r5
211; CHECK-MVEFP-NEXT:    bl __aeabi_dcmpeq
212; CHECK-MVEFP-NEXT:    cmp r0, #0
213; CHECK-MVEFP-NEXT:    csetm r0, eq
214; CHECK-MVEFP-NEXT:    cmp r6, #0
215; CHECK-MVEFP-NEXT:    csetm r1, eq
216; CHECK-MVEFP-NEXT:    vmov q0[2], q0[0], r1, r0
217; CHECK-MVEFP-NEXT:    vmov q0[3], q0[1], r1, r0
218; CHECK-MVEFP-NEXT:    vpop {d8, d9}
219; CHECK-MVEFP-NEXT:    pop {r4, r5, r6, pc}
220; CHECK-MVEFP-NEXT:    .p2align 3
221; CHECK-MVEFP-NEXT:  @ %bb.1:
222; CHECK-MVEFP-NEXT:  .LCPI6_0:
223; CHECK-MVEFP-NEXT:    .long 0 @ double 0
224; CHECK-MVEFP-NEXT:    .long 0
225entry:
226  %c = fcmp une <2 x double> %src, zeroinitializer
227  %0 = sext <2 x i1> %c to <2 x i64>
228  ret <2 x i64> %0
229}
230
231
232define arm_aapcs_vfpcc <4 x i32> @zext_v4i1_v4i32(<4 x i32> %src) {
233; CHECK-LABEL: zext_v4i1_v4i32:
234; CHECK:       @ %bb.0: @ %entry
235; CHECK-NEXT:    vmov.i32 q1, #0x0
236; CHECK-NEXT:    vmov.i32 q2, #0x1
237; CHECK-NEXT:    vcmp.s32 gt, q0, zr
238; CHECK-NEXT:    vpsel q0, q2, q1
239; CHECK-NEXT:    bx lr
240entry:
241  %c = icmp sgt <4 x i32> %src, zeroinitializer
242  %0 = zext <4 x i1> %c to <4 x i32>
243  ret <4 x i32> %0
244}
245
246define arm_aapcs_vfpcc <4 x i32> @zext_v4i1_v4f32(<4 x float> %src1, <4 x float> %src2) {
247; CHECK-MVE-LABEL: zext_v4i1_v4f32:
248; CHECK-MVE:       @ %bb.0: @ %entry
249; CHECK-MVE-NEXT:    vcmp.f32 s2, s6
250; CHECK-MVE-NEXT:    vmov.i32 q2, #0x1
251; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
252; CHECK-MVE-NEXT:    vcmp.f32 s0, s4
253; CHECK-MVE-NEXT:    csetm r0, ne
254; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
255; CHECK-MVE-NEXT:    vcmp.f32 s3, s7
256; CHECK-MVE-NEXT:    csetm r1, ne
257; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
258; CHECK-MVE-NEXT:    vcmp.f32 s1, s5
259; CHECK-MVE-NEXT:    vmov q3[2], q3[0], r1, r0
260; CHECK-MVE-NEXT:    csetm r0, ne
261; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
262; CHECK-MVE-NEXT:    csetm r1, ne
263; CHECK-MVE-NEXT:    vmov q3[3], q3[1], r1, r0
264; CHECK-MVE-NEXT:    vand q0, q3, q2
265; CHECK-MVE-NEXT:    bx lr
266;
267; CHECK-MVEFP-LABEL: zext_v4i1_v4f32:
268; CHECK-MVEFP:       @ %bb.0: @ %entry
269; CHECK-MVEFP-NEXT:    vmov.i32 q2, #0x0
270; CHECK-MVEFP-NEXT:    vmov.i32 q3, #0x1
271; CHECK-MVEFP-NEXT:    vcmp.f32 ne, q0, q1
272; CHECK-MVEFP-NEXT:    vpsel q0, q3, q2
273; CHECK-MVEFP-NEXT:    bx lr
274entry:
275  %c = fcmp une <4 x float> %src1, %src2
276  %0 = zext <4 x i1> %c to <4 x i32>
277  ret <4 x i32> %0
278}
279
280define arm_aapcs_vfpcc <8 x i16> @zext_v8i1_v8i16(<8 x i16> %src) {
281; CHECK-LABEL: zext_v8i1_v8i16:
282; CHECK:       @ %bb.0: @ %entry
283; CHECK-NEXT:    vmov.i16 q1, #0x0
284; CHECK-NEXT:    vmov.i16 q2, #0x1
285; CHECK-NEXT:    vcmp.s16 gt, q0, zr
286; CHECK-NEXT:    vpsel q0, q2, q1
287; CHECK-NEXT:    bx lr
288entry:
289  %c = icmp sgt <8 x i16> %src, zeroinitializer
290  %0 = zext <8 x i1> %c to <8 x i16>
291  ret <8 x i16> %0
292}
293
294define arm_aapcs_vfpcc <8 x i16> @zext_v8i1_v8f32(<8 x half> %src1, <8 x half> %src2) {
295; CHECK-MVE-LABEL: zext_v8i1_v8f32:
296; CHECK-MVE:       @ %bb.0: @ %entry
297; CHECK-MVE-NEXT:    .save {r4, lr}
298; CHECK-MVE-NEXT:    push {r4, lr}
299; CHECK-MVE-NEXT:    vcmp.f16 s3, s7
300; CHECK-MVE-NEXT:    vmovx.f16 s8, s6
301; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
302; CHECK-MVE-NEXT:    vmovx.f16 s10, s2
303; CHECK-MVE-NEXT:    vcmp.f16 s10, s8
304; CHECK-MVE-NEXT:    csetm r12, ne
305; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
306; CHECK-MVE-NEXT:    vcmp.f16 s2, s6
307; CHECK-MVE-NEXT:    vmovx.f16 s2, s5
308; CHECK-MVE-NEXT:    vmovx.f16 s6, s1
309; CHECK-MVE-NEXT:    csetm lr, ne
310; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
311; CHECK-MVE-NEXT:    vcmp.f16 s6, s2
312; CHECK-MVE-NEXT:    vmovx.f16 s2, s4
313; CHECK-MVE-NEXT:    vmovx.f16 s6, s0
314; CHECK-MVE-NEXT:    csetm r2, ne
315; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
316; CHECK-MVE-NEXT:    vcmp.f16 s1, s5
317; CHECK-MVE-NEXT:    csetm r3, ne
318; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
319; CHECK-MVE-NEXT:    vcmp.f16 s6, s2
320; CHECK-MVE-NEXT:    vmovx.f16 s2, s3
321; CHECK-MVE-NEXT:    csetm r0, ne
322; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
323; CHECK-MVE-NEXT:    vcmp.f16 s0, s4
324; CHECK-MVE-NEXT:    vmovx.f16 s0, s7
325; CHECK-MVE-NEXT:    csetm r1, ne
326; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
327; CHECK-MVE-NEXT:    vcmp.f16 s2, s0
328; CHECK-MVE-NEXT:    vmov.i16 q0, #0x1
329; CHECK-MVE-NEXT:    csetm r4, ne
330; CHECK-MVE-NEXT:    vmrs APSR_nzcv, fpscr
331; CHECK-MVE-NEXT:    vmov.16 q1[0], r4
332; CHECK-MVE-NEXT:    vmov.16 q1[1], r1
333; CHECK-MVE-NEXT:    vmov.16 q1[2], r0
334; CHECK-MVE-NEXT:    vmov.16 q1[3], r3
335; CHECK-MVE-NEXT:    vmov.16 q1[4], r2
336; CHECK-MVE-NEXT:    vmov.16 q1[5], lr
337; CHECK-MVE-NEXT:    vmov.16 q1[6], r12
338; CHECK-MVE-NEXT:    csetm r0, ne
339; CHECK-MVE-NEXT:    vmov.16 q1[7], r0
340; CHECK-MVE-NEXT:    vand q0, q1, q0
341; CHECK-MVE-NEXT:    pop {r4, pc}
342;
343; CHECK-MVEFP-LABEL: zext_v8i1_v8f32:
344; CHECK-MVEFP:       @ %bb.0: @ %entry
345; CHECK-MVEFP-NEXT:    vmov.i16 q2, #0x0
346; CHECK-MVEFP-NEXT:    vmov.i16 q3, #0x1
347; CHECK-MVEFP-NEXT:    vcmp.f16 ne, q0, q1
348; CHECK-MVEFP-NEXT:    vpsel q0, q3, q2
349; CHECK-MVEFP-NEXT:    bx lr
350entry:
351  %c = fcmp une <8 x half> %src1, %src2
352  %0 = zext <8 x i1> %c to <8 x i16>
353  ret <8 x i16> %0
354}
355
356define arm_aapcs_vfpcc <16 x i8> @zext_v16i1_v16i8(<16 x i8> %src) {
357; CHECK-LABEL: zext_v16i1_v16i8:
358; CHECK:       @ %bb.0: @ %entry
359; CHECK-NEXT:    vmov.i8 q1, #0x0
360; CHECK-NEXT:    vmov.i8 q2, #0x1
361; CHECK-NEXT:    vcmp.s8 gt, q0, zr
362; CHECK-NEXT:    vpsel q0, q2, q1
363; CHECK-NEXT:    bx lr
364entry:
365  %c = icmp sgt <16 x i8> %src, zeroinitializer
366  %0 = zext <16 x i1> %c to <16 x i8>
367  ret <16 x i8> %0
368}
369
370define arm_aapcs_vfpcc <2 x i64> @zext_v2i1_v2i64(<2 x i64> %src) {
371; CHECK-LABEL: zext_v2i1_v2i64:
372; CHECK:       @ %bb.0: @ %entry
373; CHECK-NEXT:    vmov r0, r1, d1
374; CHECK-NEXT:    mov.w r12, #0
375; CHECK-NEXT:    vmov r2, r3, d0
376; CHECK-NEXT:    vldr s1, .LCPI12_0
377; CHECK-NEXT:    vmov.f32 s3, s1
378; CHECK-NEXT:    rsbs r0, r0, #0
379; CHECK-NEXT:    sbcs.w r0, r12, r1
380; CHECK-NEXT:    cset r0, lt
381; CHECK-NEXT:    rsbs r1, r2, #0
382; CHECK-NEXT:    sbcs.w r1, r12, r3
383; CHECK-NEXT:    vmov s2, r0
384; CHECK-NEXT:    cset r0, lt
385; CHECK-NEXT:    vmov s0, r0
386; CHECK-NEXT:    bx lr
387; CHECK-NEXT:    .p2align 2
388; CHECK-NEXT:  @ %bb.1:
389; CHECK-NEXT:  .LCPI12_0:
390; CHECK-NEXT:    .long 0x00000000 @ float 0
391entry:
392  %c = icmp sgt <2 x i64> %src, zeroinitializer
393  %0 = zext <2 x i1> %c to <2 x i64>
394  ret <2 x i64> %0
395}
396
397define arm_aapcs_vfpcc <2 x i64> @zext_v2i1_v2f64(<2 x double> %src) {
398; CHECK-MVE-LABEL: zext_v2i1_v2f64:
399; CHECK-MVE:       @ %bb.0: @ %entry
400; CHECK-MVE-NEXT:    .save {r4, r5, r6, lr}
401; CHECK-MVE-NEXT:    push {r4, r5, r6, lr}
402; CHECK-MVE-NEXT:    .vsave {d8, d9}
403; CHECK-MVE-NEXT:    vpush {d8, d9}
404; CHECK-MVE-NEXT:    vmov q4, q0
405; CHECK-MVE-NEXT:    vldr d0, .LCPI13_0
406; CHECK-MVE-NEXT:    vmov r0, r1, d9
407; CHECK-MVE-NEXT:    vmov r4, r5, d0
408; CHECK-MVE-NEXT:    mov r2, r4
409; CHECK-MVE-NEXT:    mov r3, r5
410; CHECK-MVE-NEXT:    bl __aeabi_dcmpeq
411; CHECK-MVE-NEXT:    vmov r2, r1, d8
412; CHECK-MVE-NEXT:    adr r3, .LCPI13_1
413; CHECK-MVE-NEXT:    cmp r0, #0
414; CHECK-MVE-NEXT:    vldrw.u32 q4, [r3]
415; CHECK-MVE-NEXT:    mov r3, r5
416; CHECK-MVE-NEXT:    csetm r6, eq
417; CHECK-MVE-NEXT:    mov r0, r2
418; CHECK-MVE-NEXT:    mov r2, r4
419; CHECK-MVE-NEXT:    bl __aeabi_dcmpeq
420; CHECK-MVE-NEXT:    cmp r0, #0
421; CHECK-MVE-NEXT:    csetm r0, eq
422; CHECK-MVE-NEXT:    vmov q0[2], q0[0], r0, r6
423; CHECK-MVE-NEXT:    vand q0, q0, q4
424; CHECK-MVE-NEXT:    vpop {d8, d9}
425; CHECK-MVE-NEXT:    pop {r4, r5, r6, pc}
426; CHECK-MVE-NEXT:    .p2align 4
427; CHECK-MVE-NEXT:  @ %bb.1:
428; CHECK-MVE-NEXT:  .LCPI13_1:
429; CHECK-MVE-NEXT:    .long 1 @ 0x1
430; CHECK-MVE-NEXT:    .long 0 @ 0x0
431; CHECK-MVE-NEXT:    .long 1 @ 0x1
432; CHECK-MVE-NEXT:    .long 0 @ 0x0
433; CHECK-MVE-NEXT:  .LCPI13_0:
434; CHECK-MVE-NEXT:    .long 0 @ double 0
435; CHECK-MVE-NEXT:    .long 0
436;
437; CHECK-MVEFP-LABEL: zext_v2i1_v2f64:
438; CHECK-MVEFP:       @ %bb.0: @ %entry
439; CHECK-MVEFP-NEXT:    .save {r4, r5, r6, lr}
440; CHECK-MVEFP-NEXT:    push {r4, r5, r6, lr}
441; CHECK-MVEFP-NEXT:    .vsave {d8, d9}
442; CHECK-MVEFP-NEXT:    vpush {d8, d9}
443; CHECK-MVEFP-NEXT:    vmov q4, q0
444; CHECK-MVEFP-NEXT:    vldr d0, .LCPI13_0
445; CHECK-MVEFP-NEXT:    vmov r0, r1, d8
446; CHECK-MVEFP-NEXT:    vmov r4, r5, d0
447; CHECK-MVEFP-NEXT:    mov r2, r4
448; CHECK-MVEFP-NEXT:    mov r3, r5
449; CHECK-MVEFP-NEXT:    bl __aeabi_dcmpeq
450; CHECK-MVEFP-NEXT:    mov r6, r0
451; CHECK-MVEFP-NEXT:    vmov r0, r1, d9
452; CHECK-MVEFP-NEXT:    mov r2, r4
453; CHECK-MVEFP-NEXT:    mov r3, r5
454; CHECK-MVEFP-NEXT:    bl __aeabi_dcmpeq
455; CHECK-MVEFP-NEXT:    cmp r0, #0
456; CHECK-MVEFP-NEXT:    vldr s1, .LCPI13_1
457; CHECK-MVEFP-NEXT:    cset r0, eq
458; CHECK-MVEFP-NEXT:    cmp r6, #0
459; CHECK-MVEFP-NEXT:    vmov s2, r0
460; CHECK-MVEFP-NEXT:    cset r0, eq
461; CHECK-MVEFP-NEXT:    vmov s0, r0
462; CHECK-MVEFP-NEXT:    vmov.f32 s3, s1
463; CHECK-MVEFP-NEXT:    vpop {d8, d9}
464; CHECK-MVEFP-NEXT:    pop {r4, r5, r6, pc}
465; CHECK-MVEFP-NEXT:    .p2align 3
466; CHECK-MVEFP-NEXT:  @ %bb.1:
467; CHECK-MVEFP-NEXT:  .LCPI13_0:
468; CHECK-MVEFP-NEXT:    .long 0 @ double 0
469; CHECK-MVEFP-NEXT:    .long 0
470; CHECK-MVEFP-NEXT:  .LCPI13_1:
471; CHECK-MVEFP-NEXT:    .long 0x00000000 @ float 0
472entry:
473  %c = fcmp une <2 x double> %src, zeroinitializer
474  %0 = zext <2 x i1> %c to <2 x i64>
475  ret <2 x i64> %0
476}
477
478
479define arm_aapcs_vfpcc <4 x i32> @trunc_v4i1_v4i32(<4 x i32> %src) {
480; CHECK-LABEL: trunc_v4i1_v4i32:
481; CHECK:       @ %bb.0: @ %entry
482; CHECK-NEXT:    vmov.i32 q2, #0x1
483; CHECK-NEXT:    vmov.i32 q1, #0x0
484; CHECK-NEXT:    vand q2, q0, q2
485; CHECK-NEXT:    vcmp.i32 ne, q2, zr
486; CHECK-NEXT:    vpsel q0, q0, q1
487; CHECK-NEXT:    bx lr
488entry:
489  %0 = trunc <4 x i32> %src to <4 x i1>
490  %1 = select <4 x i1> %0, <4 x i32> %src, <4 x i32> zeroinitializer
491  ret <4 x i32> %1
492}
493
494define arm_aapcs_vfpcc <8 x i16> @trunc_v8i1_v8i16(<8 x i16> %src) {
495; CHECK-LABEL: trunc_v8i1_v8i16:
496; CHECK:       @ %bb.0: @ %entry
497; CHECK-NEXT:    vmov.i16 q2, #0x1
498; CHECK-NEXT:    vmov.i32 q1, #0x0
499; CHECK-NEXT:    vand q2, q0, q2
500; CHECK-NEXT:    vcmp.i16 ne, q2, zr
501; CHECK-NEXT:    vpsel q0, q0, q1
502; CHECK-NEXT:    bx lr
503entry:
504  %0 = trunc <8 x i16> %src to <8 x i1>
505  %1 = select <8 x i1> %0, <8 x i16> %src, <8 x i16> zeroinitializer
506  ret <8 x i16> %1
507}
508
509define arm_aapcs_vfpcc <16 x i8> @trunc_v16i1_v16i8(<16 x i8> %src) {
510; CHECK-LABEL: trunc_v16i1_v16i8:
511; CHECK:       @ %bb.0: @ %entry
512; CHECK-NEXT:    vmov.i8 q2, #0x1
513; CHECK-NEXT:    vmov.i32 q1, #0x0
514; CHECK-NEXT:    vand q2, q0, q2
515; CHECK-NEXT:    vcmp.i8 ne, q2, zr
516; CHECK-NEXT:    vpsel q0, q0, q1
517; CHECK-NEXT:    bx lr
518entry:
519  %0 = trunc <16 x i8> %src to <16 x i1>
520  %1 = select <16 x i1> %0, <16 x i8> %src, <16 x i8> zeroinitializer
521  ret <16 x i8> %1
522}
523
524define arm_aapcs_vfpcc <2 x i64> @trunc_v2i1_v2i64(<2 x i64> %src) {
525; CHECK-LABEL: trunc_v2i1_v2i64:
526; CHECK:       @ %bb.0: @ %entry
527; CHECK-NEXT:    vmov r1, s0
528; CHECK-NEXT:    movs r0, #0
529; CHECK-NEXT:    vmov.i32 q1, #0x0
530; CHECK-NEXT:    and r1, r1, #1
531; CHECK-NEXT:    rsbs r1, r1, #0
532; CHECK-NEXT:    bfi r0, r1, #0, #8
533; CHECK-NEXT:    vmov r1, s2
534; CHECK-NEXT:    and r1, r1, #1
535; CHECK-NEXT:    rsbs r1, r1, #0
536; CHECK-NEXT:    bfi r0, r1, #8, #8
537; CHECK-NEXT:    vmsr p0, r0
538; CHECK-NEXT:    vpsel q0, q0, q1
539; CHECK-NEXT:    bx lr
540entry:
541  %0 = trunc <2 x i64> %src to <2 x i1>
542  %1 = select <2 x i1> %0, <2 x i64> %src, <2 x i64> zeroinitializer
543  ret <2 x i64> %1
544}
545
546
547define arm_aapcs_vfpcc <4 x float> @uitofp_v4i1_v4f32(<4 x i32> %src) {
548; CHECK-MVE-LABEL: uitofp_v4i1_v4f32:
549; CHECK-MVE:       @ %bb.0: @ %entry
550; CHECK-MVE-NEXT:    vcmp.s32 gt, q0, zr
551; CHECK-MVE-NEXT:    vmrs r0, p0
552; CHECK-MVE-NEXT:    ubfx r2, r0, #12, #1
553; CHECK-MVE-NEXT:    ubfx r1, r0, #8, #1
554; CHECK-MVE-NEXT:    vmov s0, r2
555; CHECK-MVE-NEXT:    ubfx r2, r0, #4, #1
556; CHECK-MVE-NEXT:    and r0, r0, #1
557; CHECK-MVE-NEXT:    vcvt.f32.u32 s3, s0
558; CHECK-MVE-NEXT:    vmov s0, r1
559; CHECK-MVE-NEXT:    vcvt.f32.u32 s2, s0
560; CHECK-MVE-NEXT:    vmov s0, r2
561; CHECK-MVE-NEXT:    vcvt.f32.u32 s1, s0
562; CHECK-MVE-NEXT:    vmov s0, r0
563; CHECK-MVE-NEXT:    vcvt.f32.u32 s0, s0
564; CHECK-MVE-NEXT:    bx lr
565;
566; CHECK-MVEFP-LABEL: uitofp_v4i1_v4f32:
567; CHECK-MVEFP:       @ %bb.0: @ %entry
568; CHECK-MVEFP-NEXT:    vmov.i32 q1, #0x0
569; CHECK-MVEFP-NEXT:    vmov.f32 q2, #1.000000e+00
570; CHECK-MVEFP-NEXT:    vcmp.s32 gt, q0, zr
571; CHECK-MVEFP-NEXT:    vpsel q0, q2, q1
572; CHECK-MVEFP-NEXT:    bx lr
573entry:
574  %c = icmp sgt <4 x i32> %src, zeroinitializer
575  %0 = uitofp <4 x i1> %c to <4 x float>
576  ret <4 x float> %0
577}
578
579define arm_aapcs_vfpcc <4 x float> @sitofp_v4i1_v4f32(<4 x i32> %src) {
580; CHECK-MVE-LABEL: sitofp_v4i1_v4f32:
581; CHECK-MVE:       @ %bb.0: @ %entry
582; CHECK-MVE-NEXT:    vcmp.s32 gt, q0, zr
583; CHECK-MVE-NEXT:    vmrs r0, p0
584; CHECK-MVE-NEXT:    and r1, r0, #1
585; CHECK-MVE-NEXT:    ubfx r2, r0, #8, #1
586; CHECK-MVE-NEXT:    ubfx r3, r0, #4, #1
587; CHECK-MVE-NEXT:    ubfx r0, r0, #12, #1
588; CHECK-MVE-NEXT:    rsbs r2, r2, #0
589; CHECK-MVE-NEXT:    rsbs r0, r0, #0
590; CHECK-MVE-NEXT:    vmov s0, r0
591; CHECK-MVE-NEXT:    rsbs r0, r3, #0
592; CHECK-MVE-NEXT:    vcvt.f32.s32 s3, s0
593; CHECK-MVE-NEXT:    vmov s0, r2
594; CHECK-MVE-NEXT:    vcvt.f32.s32 s2, s0
595; CHECK-MVE-NEXT:    vmov s0, r0
596; CHECK-MVE-NEXT:    rsbs r0, r1, #0
597; CHECK-MVE-NEXT:    vcvt.f32.s32 s1, s0
598; CHECK-MVE-NEXT:    vmov s0, r0
599; CHECK-MVE-NEXT:    vcvt.f32.s32 s0, s0
600; CHECK-MVE-NEXT:    bx lr
601;
602; CHECK-MVEFP-LABEL: sitofp_v4i1_v4f32:
603; CHECK-MVEFP:       @ %bb.0: @ %entry
604; CHECK-MVEFP-NEXT:    vmov.i32 q1, #0x0
605; CHECK-MVEFP-NEXT:    vmov.f32 q2, #-1.000000e+00
606; CHECK-MVEFP-NEXT:    vcmp.s32 gt, q0, zr
607; CHECK-MVEFP-NEXT:    vpsel q0, q2, q1
608; CHECK-MVEFP-NEXT:    bx lr
609entry:
610  %c = icmp sgt <4 x i32> %src, zeroinitializer
611  %0 = sitofp <4 x i1> %c to <4 x float>
612  ret <4 x float> %0
613}
614
615define arm_aapcs_vfpcc <4 x float> @fptoui_v4i1_v4f32(<4 x float> %src) {
616; CHECK-MVE-LABEL: fptoui_v4i1_v4f32:
617; CHECK-MVE:       @ %bb.0: @ %entry
618; CHECK-MVE-NEXT:    vcvt.s32.f32 s2, s2
619; CHECK-MVE-NEXT:    vldr s10, .LCPI20_0
620; CHECK-MVE-NEXT:    vcvt.s32.f32 s6, s1
621; CHECK-MVE-NEXT:    vcvt.s32.f32 s4, s3
622; CHECK-MVE-NEXT:    vcvt.s32.f32 s0, s0
623; CHECK-MVE-NEXT:    vmov.f32 s8, #1.000000e+00
624; CHECK-MVE-NEXT:    vmov r3, s2
625; CHECK-MVE-NEXT:    vmov r2, s6
626; CHECK-MVE-NEXT:    vmov r1, s4
627; CHECK-MVE-NEXT:    vmov r0, s0
628; CHECK-MVE-NEXT:    cmp r3, #0
629; CHECK-MVE-NEXT:    vseleq.f32 s2, s10, s8
630; CHECK-MVE-NEXT:    cmp r2, #0
631; CHECK-MVE-NEXT:    vseleq.f32 s1, s10, s8
632; CHECK-MVE-NEXT:    cmp r1, #0
633; CHECK-MVE-NEXT:    vseleq.f32 s3, s10, s8
634; CHECK-MVE-NEXT:    cmp r0, #0
635; CHECK-MVE-NEXT:    vseleq.f32 s0, s10, s8
636; CHECK-MVE-NEXT:    bx lr
637; CHECK-MVE-NEXT:    .p2align 2
638; CHECK-MVE-NEXT:  @ %bb.1:
639; CHECK-MVE-NEXT:  .LCPI20_0:
640; CHECK-MVE-NEXT:    .long 0x00000000 @ float 0
641;
642; CHECK-MVEFP-LABEL: fptoui_v4i1_v4f32:
643; CHECK-MVEFP:       @ %bb.0: @ %entry
644; CHECK-MVEFP-NEXT:    vmov.i32 q1, #0x0
645; CHECK-MVEFP-NEXT:    vmov.f32 q2, #1.000000e+00
646; CHECK-MVEFP-NEXT:    vcmp.f32 ne, q0, zr
647; CHECK-MVEFP-NEXT:    vpsel q0, q2, q1
648; CHECK-MVEFP-NEXT:    bx lr
649entry:
650  %0 = fptoui <4 x float> %src to <4 x i1>
651  %s = select <4 x i1> %0, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float> zeroinitializer
652  ret <4 x float> %s
653}
654
655define arm_aapcs_vfpcc <4 x float> @fptosi_v4i1_v4f32(<4 x float> %src) {
656; CHECK-MVE-LABEL: fptosi_v4i1_v4f32:
657; CHECK-MVE:       @ %bb.0: @ %entry
658; CHECK-MVE-NEXT:    vcvt.s32.f32 s2, s2
659; CHECK-MVE-NEXT:    vldr s8, .LCPI21_0
660; CHECK-MVE-NEXT:    vcvt.s32.f32 s4, s1
661; CHECK-MVE-NEXT:    vcvt.s32.f32 s10, s3
662; CHECK-MVE-NEXT:    vcvt.s32.f32 s0, s0
663; CHECK-MVE-NEXT:    vmov.f32 s6, #1.000000e+00
664; CHECK-MVE-NEXT:    vmov r3, s2
665; CHECK-MVE-NEXT:    vmov r2, s4
666; CHECK-MVE-NEXT:    vmov r1, s10
667; CHECK-MVE-NEXT:    vmov r0, s0
668; CHECK-MVE-NEXT:    lsls r3, r3, #31
669; CHECK-MVE-NEXT:    lsl.w r2, r2, #31
670; CHECK-MVE-NEXT:    vseleq.f32 s2, s8, s6
671; CHECK-MVE-NEXT:    cmp r2, #0
672; CHECK-MVE-NEXT:    lsl.w r1, r1, #31
673; CHECK-MVE-NEXT:    vseleq.f32 s1, s8, s6
674; CHECK-MVE-NEXT:    cmp r1, #0
675; CHECK-MVE-NEXT:    lsl.w r0, r0, #31
676; CHECK-MVE-NEXT:    vseleq.f32 s3, s8, s6
677; CHECK-MVE-NEXT:    cmp r0, #0
678; CHECK-MVE-NEXT:    vseleq.f32 s0, s8, s6
679; CHECK-MVE-NEXT:    bx lr
680; CHECK-MVE-NEXT:    .p2align 2
681; CHECK-MVE-NEXT:  @ %bb.1:
682; CHECK-MVE-NEXT:  .LCPI21_0:
683; CHECK-MVE-NEXT:    .long 0x00000000 @ float 0
684;
685; CHECK-MVEFP-LABEL: fptosi_v4i1_v4f32:
686; CHECK-MVEFP:       @ %bb.0: @ %entry
687; CHECK-MVEFP-NEXT:    vmov.i32 q1, #0x0
688; CHECK-MVEFP-NEXT:    vmov.f32 q2, #1.000000e+00
689; CHECK-MVEFP-NEXT:    vcmp.f32 ne, q0, zr
690; CHECK-MVEFP-NEXT:    vpsel q0, q2, q1
691; CHECK-MVEFP-NEXT:    bx lr
692entry:
693  %0 = fptosi <4 x float> %src to <4 x i1>
694  %s = select <4 x i1> %0, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float> zeroinitializer
695  ret <4 x float> %s
696}
697
698define arm_aapcs_vfpcc <8 x half> @uitofp_v8i1_v8f16(<8 x i16> %src) {
699; CHECK-MVE-LABEL: uitofp_v8i1_v8f16:
700; CHECK-MVE:       @ %bb.0: @ %entry
701; CHECK-MVE-NEXT:    vcmp.s16 gt, q0, zr
702; CHECK-MVE-NEXT:    vmrs r0, p0
703; CHECK-MVE-NEXT:    and r1, r0, #1
704; CHECK-MVE-NEXT:    ubfx r2, r0, #2, #1
705; CHECK-MVE-NEXT:    vmov s0, r1
706; CHECK-MVE-NEXT:    ubfx r1, r0, #4, #1
707; CHECK-MVE-NEXT:    vmov s2, r2
708; CHECK-MVE-NEXT:    ubfx r2, r0, #6, #1
709; CHECK-MVE-NEXT:    vcvt.f16.u32 s2, s2
710; CHECK-MVE-NEXT:    vcvt.f16.u32 s0, s0
711; CHECK-MVE-NEXT:    vmov s4, r2
712; CHECK-MVE-NEXT:    vins.f16 s0, s2
713; CHECK-MVE-NEXT:    vmov s2, r1
714; CHECK-MVE-NEXT:    ubfx r1, r0, #8, #1
715; CHECK-MVE-NEXT:    ubfx r2, r0, #10, #1
716; CHECK-MVE-NEXT:    vcvt.f16.u32 s1, s2
717; CHECK-MVE-NEXT:    vcvt.f16.u32 s4, s4
718; CHECK-MVE-NEXT:    vmov s2, r1
719; CHECK-MVE-NEXT:    ubfx r1, r0, #12, #1
720; CHECK-MVE-NEXT:    vins.f16 s1, s4
721; CHECK-MVE-NEXT:    vmov s4, r2
722; CHECK-MVE-NEXT:    ubfx r0, r0, #14, #1
723; CHECK-MVE-NEXT:    vcvt.f16.u32 s4, s4
724; CHECK-MVE-NEXT:    vcvt.f16.u32 s2, s2
725; CHECK-MVE-NEXT:    vins.f16 s2, s4
726; CHECK-MVE-NEXT:    vmov s4, r0
727; CHECK-MVE-NEXT:    vmov s6, r1
728; CHECK-MVE-NEXT:    vcvt.f16.u32 s4, s4
729; CHECK-MVE-NEXT:    vcvt.f16.u32 s3, s6
730; CHECK-MVE-NEXT:    vins.f16 s3, s4
731; CHECK-MVE-NEXT:    bx lr
732;
733; CHECK-MVEFP-LABEL: uitofp_v8i1_v8f16:
734; CHECK-MVEFP:       @ %bb.0: @ %entry
735; CHECK-MVEFP-NEXT:    vmov.i16 q1, #0x0
736; CHECK-MVEFP-NEXT:    vmov.i16 q2, #0x3c00
737; CHECK-MVEFP-NEXT:    vcmp.s16 gt, q0, zr
738; CHECK-MVEFP-NEXT:    vpsel q0, q2, q1
739; CHECK-MVEFP-NEXT:    bx lr
740entry:
741  %c = icmp sgt <8 x i16> %src, zeroinitializer
742  %0 = uitofp <8 x i1> %c to <8 x half>
743  ret <8 x half> %0
744}
745
746define arm_aapcs_vfpcc <8 x half> @sitofp_v8i1_v8f16(<8 x i16> %src) {
747; CHECK-MVE-LABEL: sitofp_v8i1_v8f16:
748; CHECK-MVE:       @ %bb.0: @ %entry
749; CHECK-MVE-NEXT:    vcmp.s16 gt, q0, zr
750; CHECK-MVE-NEXT:    vmrs r0, p0
751; CHECK-MVE-NEXT:    and r1, r0, #1
752; CHECK-MVE-NEXT:    ubfx r2, r0, #2, #1
753; CHECK-MVE-NEXT:    rsbs r1, r1, #0
754; CHECK-MVE-NEXT:    rsbs r2, r2, #0
755; CHECK-MVE-NEXT:    vmov s0, r2
756; CHECK-MVE-NEXT:    ubfx r2, r0, #6, #1
757; CHECK-MVE-NEXT:    vcvt.f16.s32 s2, s0
758; CHECK-MVE-NEXT:    vmov s0, r1
759; CHECK-MVE-NEXT:    ubfx r1, r0, #4, #1
760; CHECK-MVE-NEXT:    rsbs r2, r2, #0
761; CHECK-MVE-NEXT:    vcvt.f16.s32 s0, s0
762; CHECK-MVE-NEXT:    rsbs r1, r1, #0
763; CHECK-MVE-NEXT:    vins.f16 s0, s2
764; CHECK-MVE-NEXT:    vmov s2, r2
765; CHECK-MVE-NEXT:    ubfx r2, r0, #10, #1
766; CHECK-MVE-NEXT:    vmov s4, r1
767; CHECK-MVE-NEXT:    ubfx r1, r0, #8, #1
768; CHECK-MVE-NEXT:    rsbs r2, r2, #0
769; CHECK-MVE-NEXT:    vcvt.f16.s32 s2, s2
770; CHECK-MVE-NEXT:    vcvt.f16.s32 s1, s4
771; CHECK-MVE-NEXT:    rsbs r1, r1, #0
772; CHECK-MVE-NEXT:    vins.f16 s1, s2
773; CHECK-MVE-NEXT:    vmov s2, r2
774; CHECK-MVE-NEXT:    vcvt.f16.s32 s4, s2
775; CHECK-MVE-NEXT:    vmov s2, r1
776; CHECK-MVE-NEXT:    ubfx r1, r0, #12, #1
777; CHECK-MVE-NEXT:    ubfx r0, r0, #14, #1
778; CHECK-MVE-NEXT:    rsbs r1, r1, #0
779; CHECK-MVE-NEXT:    rsbs r0, r0, #0
780; CHECK-MVE-NEXT:    vcvt.f16.s32 s2, s2
781; CHECK-MVE-NEXT:    vins.f16 s2, s4
782; CHECK-MVE-NEXT:    vmov s4, r0
783; CHECK-MVE-NEXT:    vmov s6, r1
784; CHECK-MVE-NEXT:    vcvt.f16.s32 s4, s4
785; CHECK-MVE-NEXT:    vcvt.f16.s32 s3, s6
786; CHECK-MVE-NEXT:    vins.f16 s3, s4
787; CHECK-MVE-NEXT:    bx lr
788;
789; CHECK-MVEFP-LABEL: sitofp_v8i1_v8f16:
790; CHECK-MVEFP:       @ %bb.0: @ %entry
791; CHECK-MVEFP-NEXT:    vmov.i16 q1, #0x0
792; CHECK-MVEFP-NEXT:    vmov.i16 q2, #0xbc00
793; CHECK-MVEFP-NEXT:    vcmp.s16 gt, q0, zr
794; CHECK-MVEFP-NEXT:    vpsel q0, q2, q1
795; CHECK-MVEFP-NEXT:    bx lr
796entry:
797  %c = icmp sgt <8 x i16> %src, zeroinitializer
798  %0 = sitofp <8 x i1> %c to <8 x half>
799  ret <8 x half> %0
800}
801
802define arm_aapcs_vfpcc <8 x half> @fptoui_v8i1_v8f16(<8 x half> %src) {
803; CHECK-MVE-LABEL: fptoui_v8i1_v8f16:
804; CHECK-MVE:       @ %bb.0: @ %entry
805; CHECK-MVE-NEXT:    vcvt.s32.f16 s4, s0
806; CHECK-MVE-NEXT:    vmovx.f16 s0, s0
807; CHECK-MVE-NEXT:    vcvt.s32.f16 s0, s0
808; CHECK-MVE-NEXT:    vmov r0, s4
809; CHECK-MVE-NEXT:    vmov r1, s0
810; CHECK-MVE-NEXT:    vldr.16 s8, .LCPI24_0
811; CHECK-MVE-NEXT:    vmov.f16 s6, #1.000000e+00
812; CHECK-MVE-NEXT:    vmovx.f16 s10, s1
813; CHECK-MVE-NEXT:    vcvt.s32.f16 s10, s10
814; CHECK-MVE-NEXT:    cmp r1, #0
815; CHECK-MVE-NEXT:    vmov r1, s10
816; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s6
817; CHECK-MVE-NEXT:    cmp r0, #0
818; CHECK-MVE-NEXT:    vseleq.f16 s0, s8, s6
819; CHECK-MVE-NEXT:    vmovx.f16 s10, s3
820; CHECK-MVE-NEXT:    vins.f16 s0, s4
821; CHECK-MVE-NEXT:    vcvt.s32.f16 s4, s1
822; CHECK-MVE-NEXT:    vmov r0, s4
823; CHECK-MVE-NEXT:    vcvt.s32.f16 s10, s10
824; CHECK-MVE-NEXT:    cmp r1, #0
825; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s6
826; CHECK-MVE-NEXT:    cmp r0, #0
827; CHECK-MVE-NEXT:    vseleq.f16 s1, s8, s6
828; CHECK-MVE-NEXT:    vins.f16 s1, s4
829; CHECK-MVE-NEXT:    vcvt.s32.f16 s4, s2
830; CHECK-MVE-NEXT:    vmovx.f16 s2, s2
831; CHECK-MVE-NEXT:    vmov r0, s4
832; CHECK-MVE-NEXT:    vcvt.s32.f16 s2, s2
833; CHECK-MVE-NEXT:    vmov r1, s2
834; CHECK-MVE-NEXT:    cmp r1, #0
835; CHECK-MVE-NEXT:    vmov r1, s10
836; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s6
837; CHECK-MVE-NEXT:    cmp r0, #0
838; CHECK-MVE-NEXT:    vseleq.f16 s2, s8, s6
839; CHECK-MVE-NEXT:    vins.f16 s2, s4
840; CHECK-MVE-NEXT:    vcvt.s32.f16 s4, s3
841; CHECK-MVE-NEXT:    vmov r0, s4
842; CHECK-MVE-NEXT:    cmp r1, #0
843; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s6
844; CHECK-MVE-NEXT:    cmp r0, #0
845; CHECK-MVE-NEXT:    vseleq.f16 s3, s8, s6
846; CHECK-MVE-NEXT:    vins.f16 s3, s4
847; CHECK-MVE-NEXT:    bx lr
848; CHECK-MVE-NEXT:    .p2align 1
849; CHECK-MVE-NEXT:  @ %bb.1:
850; CHECK-MVE-NEXT:  .LCPI24_0:
851; CHECK-MVE-NEXT:    .short 0x0000 @ half 0
852;
853; CHECK-MVEFP-LABEL: fptoui_v8i1_v8f16:
854; CHECK-MVEFP:       @ %bb.0: @ %entry
855; CHECK-MVEFP-NEXT:    vmov.i32 q1, #0x0
856; CHECK-MVEFP-NEXT:    vmov.i16 q2, #0x3c00
857; CHECK-MVEFP-NEXT:    vcmp.f16 ne, q0, zr
858; CHECK-MVEFP-NEXT:    vpsel q0, q2, q1
859; CHECK-MVEFP-NEXT:    bx lr
860entry:
861  %0 = fptoui <8 x half> %src to <8 x i1>
862  %s = select <8 x i1> %0, <8 x half> <half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0>, <8 x half> zeroinitializer
863  ret <8 x half> %s
864}
865
866define arm_aapcs_vfpcc <8 x half> @fptosi_v8i1_v8f16(<8 x half> %src) {
867; CHECK-MVE-LABEL: fptosi_v8i1_v8f16:
868; CHECK-MVE:       @ %bb.0: @ %entry
869; CHECK-MVE-NEXT:    vcvt.s32.f16 s4, s0
870; CHECK-MVE-NEXT:    vmovx.f16 s0, s0
871; CHECK-MVE-NEXT:    vcvt.s32.f16 s0, s0
872; CHECK-MVE-NEXT:    vmov r0, s4
873; CHECK-MVE-NEXT:    vmov r1, s0
874; CHECK-MVE-NEXT:    vldr.16 s8, .LCPI25_0
875; CHECK-MVE-NEXT:    vmov.f16 s6, #1.000000e+00
876; CHECK-MVE-NEXT:    vmovx.f16 s10, s1
877; CHECK-MVE-NEXT:    vcvt.s32.f16 s10, s10
878; CHECK-MVE-NEXT:    lsls r0, r0, #31
879; CHECK-MVE-NEXT:    lsls r1, r1, #31
880; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s6
881; CHECK-MVE-NEXT:    cmp r0, #0
882; CHECK-MVE-NEXT:    vseleq.f16 s0, s8, s6
883; CHECK-MVE-NEXT:    vmov r1, s10
884; CHECK-MVE-NEXT:    vins.f16 s0, s4
885; CHECK-MVE-NEXT:    vcvt.s32.f16 s4, s1
886; CHECK-MVE-NEXT:    vmov r0, s4
887; CHECK-MVE-NEXT:    vmovx.f16 s10, s3
888; CHECK-MVE-NEXT:    vcvt.s32.f16 s10, s10
889; CHECK-MVE-NEXT:    lsls r1, r1, #31
890; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s6
891; CHECK-MVE-NEXT:    lsls r0, r0, #31
892; CHECK-MVE-NEXT:    cmp r0, #0
893; CHECK-MVE-NEXT:    vseleq.f16 s1, s8, s6
894; CHECK-MVE-NEXT:    vins.f16 s1, s4
895; CHECK-MVE-NEXT:    vcvt.s32.f16 s4, s2
896; CHECK-MVE-NEXT:    vmovx.f16 s2, s2
897; CHECK-MVE-NEXT:    vmov r0, s4
898; CHECK-MVE-NEXT:    vcvt.s32.f16 s2, s2
899; CHECK-MVE-NEXT:    vmov r1, s2
900; CHECK-MVE-NEXT:    lsls r0, r0, #31
901; CHECK-MVE-NEXT:    lsls r1, r1, #31
902; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s6
903; CHECK-MVE-NEXT:    cmp r0, #0
904; CHECK-MVE-NEXT:    vseleq.f16 s2, s8, s6
905; CHECK-MVE-NEXT:    vmov r1, s10
906; CHECK-MVE-NEXT:    vins.f16 s2, s4
907; CHECK-MVE-NEXT:    vcvt.s32.f16 s4, s3
908; CHECK-MVE-NEXT:    vmov r0, s4
909; CHECK-MVE-NEXT:    lsls r1, r1, #31
910; CHECK-MVE-NEXT:    vseleq.f16 s4, s8, s6
911; CHECK-MVE-NEXT:    lsls r0, r0, #31
912; CHECK-MVE-NEXT:    cmp r0, #0
913; CHECK-MVE-NEXT:    vseleq.f16 s3, s8, s6
914; CHECK-MVE-NEXT:    vins.f16 s3, s4
915; CHECK-MVE-NEXT:    bx lr
916; CHECK-MVE-NEXT:    .p2align 1
917; CHECK-MVE-NEXT:  @ %bb.1:
918; CHECK-MVE-NEXT:  .LCPI25_0:
919; CHECK-MVE-NEXT:    .short 0x0000 @ half 0
920;
921; CHECK-MVEFP-LABEL: fptosi_v8i1_v8f16:
922; CHECK-MVEFP:       @ %bb.0: @ %entry
923; CHECK-MVEFP-NEXT:    vmov.i32 q1, #0x0
924; CHECK-MVEFP-NEXT:    vmov.i16 q2, #0x3c00
925; CHECK-MVEFP-NEXT:    vcmp.f16 ne, q0, zr
926; CHECK-MVEFP-NEXT:    vpsel q0, q2, q1
927; CHECK-MVEFP-NEXT:    bx lr
928entry:
929  %0 = fptosi <8 x half> %src to <8 x i1>
930  %s = select <8 x i1> %0, <8 x half> <half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0>, <8 x half> zeroinitializer
931  ret <8 x half> %s
932}
933
934
935define arm_aapcs_vfpcc <2 x double> @uitofp_v2i1_v2f64(<2 x i64> %src) {
936; CHECK-LABEL: uitofp_v2i1_v2f64:
937; CHECK:       @ %bb.0: @ %entry
938; CHECK-NEXT:    .save {r4, lr}
939; CHECK-NEXT:    push {r4, lr}
940; CHECK-NEXT:    .vsave {d8, d9}
941; CHECK-NEXT:    vpush {d8, d9}
942; CHECK-NEXT:    vmov q4, q0
943; CHECK-NEXT:    movs r4, #0
944; CHECK-NEXT:    vmov r0, r1, d9
945; CHECK-NEXT:    rsbs r0, r0, #0
946; CHECK-NEXT:    sbcs.w r0, r4, r1
947; CHECK-NEXT:    cset r0, lt
948; CHECK-NEXT:    bl __aeabi_ui2d
949; CHECK-NEXT:    vmov r2, r3, d8
950; CHECK-NEXT:    vmov d9, r0, r1
951; CHECK-NEXT:    rsbs r2, r2, #0
952; CHECK-NEXT:    sbcs.w r2, r4, r3
953; CHECK-NEXT:    cset r2, lt
954; CHECK-NEXT:    mov r0, r2
955; CHECK-NEXT:    bl __aeabi_ui2d
956; CHECK-NEXT:    vmov d8, r0, r1
957; CHECK-NEXT:    vmov q0, q4
958; CHECK-NEXT:    vpop {d8, d9}
959; CHECK-NEXT:    pop {r4, pc}
960entry:
961  %c = icmp sgt <2 x i64> %src, zeroinitializer
962  %0 = uitofp <2 x i1> %c to <2 x double>
963  ret <2 x double> %0
964}
965
966define arm_aapcs_vfpcc <2 x double> @sitofp_v2i1_v2f64(<2 x i64> %src) {
967; CHECK-LABEL: sitofp_v2i1_v2f64:
968; CHECK:       @ %bb.0: @ %entry
969; CHECK-NEXT:    .save {r4, lr}
970; CHECK-NEXT:    push {r4, lr}
971; CHECK-NEXT:    .vsave {d8, d9}
972; CHECK-NEXT:    vpush {d8, d9}
973; CHECK-NEXT:    vmov q4, q0
974; CHECK-NEXT:    movs r4, #0
975; CHECK-NEXT:    vmov r0, r1, d9
976; CHECK-NEXT:    rsbs r0, r0, #0
977; CHECK-NEXT:    sbcs.w r0, r4, r1
978; CHECK-NEXT:    csetm r0, lt
979; CHECK-NEXT:    bl __aeabi_i2d
980; CHECK-NEXT:    vmov r2, r3, d8
981; CHECK-NEXT:    vmov d9, r0, r1
982; CHECK-NEXT:    rsbs r2, r2, #0
983; CHECK-NEXT:    sbcs.w r2, r4, r3
984; CHECK-NEXT:    csetm r2, lt
985; CHECK-NEXT:    mov r0, r2
986; CHECK-NEXT:    bl __aeabi_i2d
987; CHECK-NEXT:    vmov d8, r0, r1
988; CHECK-NEXT:    vmov q0, q4
989; CHECK-NEXT:    vpop {d8, d9}
990; CHECK-NEXT:    pop {r4, pc}
991entry:
992  %c = icmp sgt <2 x i64> %src, zeroinitializer
993  %0 = sitofp <2 x i1> %c to <2 x double>
994  ret <2 x double> %0
995}
996
997define arm_aapcs_vfpcc <2 x double> @fptoui_v2i1_v2f64(<2 x double> %src) {
998; CHECK-LABEL: fptoui_v2i1_v2f64:
999; CHECK:       @ %bb.0: @ %entry
1000; CHECK-NEXT:    .save {r4, lr}
1001; CHECK-NEXT:    push {r4, lr}
1002; CHECK-NEXT:    .vsave {d8, d9, d10, d11}
1003; CHECK-NEXT:    vpush {d8, d9, d10, d11}
1004; CHECK-NEXT:    vmov q4, q0
1005; CHECK-NEXT:    vmov r0, r1, d8
1006; CHECK-NEXT:    bl __aeabi_d2iz
1007; CHECK-NEXT:    vmov r2, r1, d9
1008; CHECK-NEXT:    movs r4, #0
1009; CHECK-NEXT:    rsbs r0, r0, #0
1010; CHECK-NEXT:    adr r3, .LCPI28_0
1011; CHECK-NEXT:    bfi r4, r0, #0, #8
1012; CHECK-NEXT:    vmov.i32 q4, #0x0
1013; CHECK-NEXT:    vldrw.u32 q5, [r3]
1014; CHECK-NEXT:    mov r0, r2
1015; CHECK-NEXT:    bl __aeabi_d2iz
1016; CHECK-NEXT:    rsbs r0, r0, #0
1017; CHECK-NEXT:    bfi r4, r0, #8, #8
1018; CHECK-NEXT:    vmsr p0, r4
1019; CHECK-NEXT:    vpsel q0, q5, q4
1020; CHECK-NEXT:    vpop {d8, d9, d10, d11}
1021; CHECK-NEXT:    pop {r4, pc}
1022; CHECK-NEXT:    .p2align 4
1023; CHECK-NEXT:  @ %bb.1:
1024; CHECK-NEXT:  .LCPI28_0:
1025; CHECK-NEXT:    .long 0 @ double 1
1026; CHECK-NEXT:    .long 1072693248
1027; CHECK-NEXT:    .long 0 @ double 1
1028; CHECK-NEXT:    .long 1072693248
1029entry:
1030  %0 = fptoui <2 x double> %src to <2 x i1>
1031  %s = select <2 x i1> %0, <2 x double> <double 1.0, double 1.0>, <2 x double> zeroinitializer
1032  ret <2 x double> %s
1033}
1034
1035define arm_aapcs_vfpcc <2 x double> @fptosi_v2i1_v2f64(<2 x double> %src) {
1036; CHECK-LABEL: fptosi_v2i1_v2f64:
1037; CHECK:       @ %bb.0: @ %entry
1038; CHECK-NEXT:    .save {r4, lr}
1039; CHECK-NEXT:    push {r4, lr}
1040; CHECK-NEXT:    .vsave {d8, d9, d10, d11}
1041; CHECK-NEXT:    vpush {d8, d9, d10, d11}
1042; CHECK-NEXT:    vmov q4, q0
1043; CHECK-NEXT:    vmov r0, r1, d8
1044; CHECK-NEXT:    bl __aeabi_d2iz
1045; CHECK-NEXT:    vmov r2, r1, d9
1046; CHECK-NEXT:    movs r4, #0
1047; CHECK-NEXT:    adr r3, .LCPI29_0
1048; CHECK-NEXT:    bfi r4, r0, #0, #8
1049; CHECK-NEXT:    vmov.i32 q4, #0x0
1050; CHECK-NEXT:    vldrw.u32 q5, [r3]
1051; CHECK-NEXT:    mov r0, r2
1052; CHECK-NEXT:    bl __aeabi_d2iz
1053; CHECK-NEXT:    bfi r4, r0, #8, #8
1054; CHECK-NEXT:    vmsr p0, r4
1055; CHECK-NEXT:    vpsel q0, q5, q4
1056; CHECK-NEXT:    vpop {d8, d9, d10, d11}
1057; CHECK-NEXT:    pop {r4, pc}
1058; CHECK-NEXT:    .p2align 4
1059; CHECK-NEXT:  @ %bb.1:
1060; CHECK-NEXT:  .LCPI29_0:
1061; CHECK-NEXT:    .long 0 @ double 1
1062; CHECK-NEXT:    .long 1072693248
1063; CHECK-NEXT:    .long 0 @ double 1
1064; CHECK-NEXT:    .long 1072693248
1065entry:
1066  %0 = fptosi <2 x double> %src to <2 x i1>
1067  %s = select <2 x i1> %0, <2 x double> <double 1.0, double 1.0>, <2 x double> zeroinitializer
1068  ret <2 x double> %s
1069}
1070