xref: /llvm-project/llvm/test/CodeGen/Thumb2/mve-pred-build-const.ll (revision 255ad7342436ff4901d39579f694857f83386dad) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
3
4
5define arm_aapcs_vfpcc <4 x i32> @build_true_v4i1(<4 x i32> %a, <4 x i32> %b) {
6; CHECK-LABEL: build_true_v4i1:
7; CHECK:       @ %bb.0: @ %entry
8; CHECK-NEXT:    bx lr
9entry:
10  %s = select <4 x i1> <i1 1, i1 1, i1 1, i1 1>, <4 x i32> %a, <4 x i32> %b
11  ret <4 x i32> %s
12}
13
14define arm_aapcs_vfpcc <4 x i32> @build_false_v4i1(<4 x i32> %a, <4 x i32> %b) {
15; CHECK-LABEL: build_false_v4i1:
16; CHECK:       @ %bb.0: @ %entry
17; CHECK-NEXT:    vmov q0, q1
18; CHECK-NEXT:    bx lr
19entry:
20  %s = select <4 x i1> <i1 0, i1 0, i1 0, i1 0>, <4 x i32> %a, <4 x i32> %b
21  ret <4 x i32> %s
22}
23
24define arm_aapcs_vfpcc <4 x i32> @build_upper_v4i1(<4 x i32> %a, <4 x i32> %b) {
25; CHECK-LABEL: build_upper_v4i1:
26; CHECK:       @ %bb.0: @ %entry
27; CHECK-NEXT:    mov.w r0, #65280
28; CHECK-NEXT:    vmsr p0, r0
29; CHECK-NEXT:    vpsel q0, q0, q1
30; CHECK-NEXT:    bx lr
31entry:
32  %s = select <4 x i1> <i1 0, i1 0, i1 1, i1 1>, <4 x i32> %a, <4 x i32> %b
33  ret <4 x i32> %s
34}
35
36define arm_aapcs_vfpcc <4 x i32> @build_lower_v4i1(<4 x i32> %a, <4 x i32> %b) {
37; CHECK-LABEL: build_lower_v4i1:
38; CHECK:       @ %bb.0: @ %entry
39; CHECK-NEXT:    movs r0, #255
40; CHECK-NEXT:    vmsr p0, r0
41; CHECK-NEXT:    vpsel q0, q0, q1
42; CHECK-NEXT:    bx lr
43entry:
44  %s = select <4 x i1> <i1 1, i1 1, i1 0, i1 0>, <4 x i32> %a, <4 x i32> %b
45  ret <4 x i32> %s
46}
47
48
49define arm_aapcs_vfpcc <8 x i16> @build_true_v8i1(<8 x i16> %a, <8 x i16> %b) {
50; CHECK-LABEL: build_true_v8i1:
51; CHECK:       @ %bb.0: @ %entry
52; CHECK-NEXT:    bx lr
53entry:
54  %s = select <8 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <8 x i16> %a, <8 x i16> %b
55  ret <8 x i16> %s
56}
57
58define arm_aapcs_vfpcc <8 x i16> @build_false_v8i1(<8 x i16> %a, <8 x i16> %b) {
59; CHECK-LABEL: build_false_v8i1:
60; CHECK:       @ %bb.0: @ %entry
61; CHECK-NEXT:    vmov q0, q1
62; CHECK-NEXT:    bx lr
63entry:
64  %s = select <8 x i1> <i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0>, <8 x i16> %a, <8 x i16> %b
65  ret <8 x i16> %s
66}
67
68define arm_aapcs_vfpcc <8 x i16> @build_upper_v8i1(<8 x i16> %a, <8 x i16> %b) {
69; CHECK-LABEL: build_upper_v8i1:
70; CHECK:       @ %bb.0: @ %entry
71; CHECK-NEXT:    mov.w r0, #65280
72; CHECK-NEXT:    vmsr p0, r0
73; CHECK-NEXT:    vpsel q0, q0, q1
74; CHECK-NEXT:    bx lr
75entry:
76  %s = select <8 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1>, <8 x i16> %a, <8 x i16> %b
77  ret <8 x i16> %s
78}
79
80define arm_aapcs_vfpcc <8 x i16> @build_lower_v8i1(<8 x i16> %a, <8 x i16> %b) {
81; CHECK-LABEL: build_lower_v8i1:
82; CHECK:       @ %bb.0: @ %entry
83; CHECK-NEXT:    movs r0, #255
84; CHECK-NEXT:    vmsr p0, r0
85; CHECK-NEXT:    vpsel q0, q0, q1
86; CHECK-NEXT:    bx lr
87entry:
88  %s = select <8 x i1> <i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0>, <8 x i16> %a, <8 x i16> %b
89  ret <8 x i16> %s
90}
91
92
93define arm_aapcs_vfpcc <16 x i8> @build_true_v16i1(<16 x i8> %a, <16 x i8> %b) {
94; CHECK-LABEL: build_true_v16i1:
95; CHECK:       @ %bb.0: @ %entry
96; CHECK-NEXT:    bx lr
97entry:
98  %s = select <16 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <16 x i8> %a, <16 x i8> %b
99  ret <16 x i8> %s
100}
101
102define arm_aapcs_vfpcc <16 x i8> @build_false_v16i1(<16 x i8> %a, <16 x i8> %b) {
103; CHECK-LABEL: build_false_v16i1:
104; CHECK:       @ %bb.0: @ %entry
105; CHECK-NEXT:    vmov q0, q1
106; CHECK-NEXT:    bx lr
107entry:
108  %s = select <16 x i1> <i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0>, <16 x i8> %a, <16 x i8> %b
109  ret <16 x i8> %s
110}
111
112define arm_aapcs_vfpcc <16 x i8> @build_upper_v16i1(<16 x i8> %a, <16 x i8> %b) {
113; CHECK-LABEL: build_upper_v16i1:
114; CHECK:       @ %bb.0: @ %entry
115; CHECK-NEXT:    mov.w r0, #65280
116; CHECK-NEXT:    vmsr p0, r0
117; CHECK-NEXT:    vpsel q0, q0, q1
118; CHECK-NEXT:    bx lr
119entry:
120  %s = select <16 x i1> <i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <16 x i8> %a, <16 x i8> %b
121  ret <16 x i8> %s
122}
123
124define arm_aapcs_vfpcc <16 x i8> @build_lower_v16i1(<16 x i8> %a, <16 x i8> %b) {
125; CHECK-LABEL: build_lower_v16i1:
126; CHECK:       @ %bb.0: @ %entry
127; CHECK-NEXT:    movs r0, #255
128; CHECK-NEXT:    vmsr p0, r0
129; CHECK-NEXT:    vpsel q0, q0, q1
130; CHECK-NEXT:    bx lr
131entry:
132  %s = select <16 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0>, <16 x i8> %a, <16 x i8> %b
133  ret <16 x i8> %s
134}
135
136
137define arm_aapcs_vfpcc <2 x i64> @build_true_v2i1(<2 x i64> %a, <2 x i64> %b) {
138; CHECK-LABEL: build_true_v2i1:
139; CHECK:       @ %bb.0: @ %entry
140; CHECK-NEXT:    bx lr
141entry:
142  %s = select <2 x i1> <i1 1, i1 1>, <2 x i64> %a, <2 x i64> %b
143  ret <2 x i64> %s
144}
145
146define arm_aapcs_vfpcc <2 x i64> @build_false_v2i1(<2 x i64> %a, <2 x i64> %b) {
147; CHECK-LABEL: build_false_v2i1:
148; CHECK:       @ %bb.0: @ %entry
149; CHECK-NEXT:    vmov q0, q1
150; CHECK-NEXT:    bx lr
151entry:
152  %s = select <2 x i1> <i1 0, i1 0>, <2 x i64> %a, <2 x i64> %b
153  ret <2 x i64> %s
154}
155
156define arm_aapcs_vfpcc <2 x i64> @build_upper_v2i1(<2 x i64> %a, <2 x i64> %b) {
157; CHECK-LABEL: build_upper_v2i1:
158; CHECK:       @ %bb.0: @ %entry
159; CHECK-NEXT:    mov.w r0, #65280
160; CHECK-NEXT:    vmsr p0, r0
161; CHECK-NEXT:    vpsel q0, q0, q1
162; CHECK-NEXT:    bx lr
163entry:
164  %s = select <2 x i1> <i1 0, i1 1>, <2 x i64> %a, <2 x i64> %b
165  ret <2 x i64> %s
166}
167
168define arm_aapcs_vfpcc <2 x i64> @build_lower_v2i1(<2 x i64> %a, <2 x i64> %b) {
169; CHECK-LABEL: build_lower_v2i1:
170; CHECK:       @ %bb.0: @ %entry
171; CHECK-NEXT:    movs r0, #255
172; CHECK-NEXT:    vmsr p0, r0
173; CHECK-NEXT:    vpsel q0, q0, q1
174; CHECK-NEXT:    bx lr
175entry:
176  %s = select <2 x i1> <i1 1, i1 0>, <2 x i64> %a, <2 x i64> %b
177  ret <2 x i64> %s
178}
179