1; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -verify-machineinstrs 2; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -verify-machineinstrs -O0 3target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" 4target triple = "thumbv7-apple-darwin10" 5 6; This function would crash LiveIntervalAnalysis by creating a chain of 4 INSERT_SUBREGs of the same register. 7define arm_apcscc void @NEON_vst4q_u32(ptr nocapture %sp0, ptr nocapture %sp1, ptr nocapture %sp2, ptr nocapture %sp3, ptr %dp) nounwind { 8entry: 9 %0 = load <4 x i32>, ptr %sp0, align 16 ; <<4 x i32>> [#uses=1] 10 %1 = load <4 x i32>, ptr %sp1, align 16 ; <<4 x i32>> [#uses=1] 11 %2 = load <4 x i32>, ptr %sp2, align 16 ; <<4 x i32>> [#uses=1] 12 %3 = load <4 x i32>, ptr %sp3, align 16 ; <<4 x i32>> [#uses=1] 13 tail call void @llvm.arm.neon.vst4.p0.v4i32(ptr %dp, <4 x i32> %0, <4 x i32> %1, <4 x i32> %2, <4 x i32> %3, i32 1) 14 ret void 15} 16 17declare void @llvm.arm.neon.vst4.p0.v4i32(ptr, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind 18 19@sbuf = common global [16 x i32] zeroinitializer, align 16 ; <ptr> [#uses=5] 20@dbuf = common global [16 x i32] zeroinitializer ; <ptr> [#uses=2] 21 22; This function creates 4 chained INSERT_SUBREGS and then invokes the register scavenger. 23; The first INSERT_SUBREG needs an <undef> use operand for that to work. 24define arm_apcscc i32 @main() nounwind { 25bb.nph: 26 br label %bb 27 28bb: ; preds = %bb, %bb.nph 29 %0 = phi i32 [ 0, %bb.nph ], [ %1, %bb ] ; <i32> [#uses=4] 30 %scevgep = getelementptr [16 x i32], ptr @sbuf, i32 0, i32 %0 ; <ptr> [#uses=1] 31 %scevgep5 = getelementptr [16 x i32], ptr @dbuf, i32 0, i32 %0 ; <ptr> [#uses=1] 32 store i32 %0, ptr %scevgep, align 4 33 store i32 -1, ptr %scevgep5, align 4 34 %1 = add nsw i32 %0, 1 ; <i32> [#uses=2] 35 %exitcond = icmp eq i32 %1, 16 ; <i1> [#uses=1] 36 br i1 %exitcond, label %bb2, label %bb 37 38bb2: ; preds = %bb 39 %2 = load <4 x i32>, ptr @sbuf, align 16 ; <<4 x i32>> [#uses=1] 40 %3 = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @sbuf, i32 0, i32 4), align 16 ; <<4 x i32>> [#uses=1] 41 %4 = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @sbuf, i32 0, i32 8), align 16 ; <<4 x i32>> [#uses=1] 42 %5 = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @sbuf, i32 0, i32 12), align 16 ; <<4 x i32>> [#uses=1] 43 tail call void @llvm.arm.neon.vst4.p0.v4i32(ptr @dbuf, <4 x i32> %2, <4 x i32> %3, <4 x i32> %4, <4 x i32> %5, i32 1) nounwind 44 ret i32 0 45} 46 47; PR12389 48; Make sure the DPair register class can spill. 49define void @pr12389(ptr %p) nounwind ssp { 50entry: 51 %vld1 = tail call <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr %p, i32 1) 52 tail call void asm sideeffect "", "~{q0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7},~{q8},~{q9},~{q10},~{q11},~{q12},~{q13},~{q14},~{q15}"() nounwind 53 tail call void @llvm.arm.neon.vst1.p0.v4f32(ptr %p, <4 x float> %vld1, i32 1) 54 ret void 55} 56 57declare <4 x float> @llvm.arm.neon.vld1.v4f32.p0(ptr, i32) nounwind readonly 58 59declare void @llvm.arm.neon.vst1.p0.v4f32(ptr, <4 x float>, i32) nounwind 60 61; <rdar://problem/11101911> 62; When an strd is expanded into two str instructions, make sure the first str 63; doesn't kill the base register. This can happen if the base register is the 64; same as the data register. 65%class = type { ptr, ptr, i32 } 66define void @f11101911(ptr %this, i32 %num) ssp align 2 { 67entry: 68 %p1 = getelementptr inbounds %class, ptr %this, i32 0, i32 1 69 %p2 = getelementptr inbounds %class, ptr %this, i32 0, i32 2 70 tail call void asm sideeffect "", "~{r1},~{r3},~{r5},~{r11},~{r13}"() nounwind 71 store ptr %this, ptr %p1, align 4 72 store i32 %num, ptr %p2, align 4 73 ret void 74} 75 76; Check RAFast handling of inline assembly with many dense clobbers. 77; The large tuple aliases of the vector registers can cause problems. 78define void @rdar13249625(ptr nocapture %p) nounwind { 79 %1 = tail call double asm sideeffect "@ $0", "=w,~{d0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7},~{q8},~{q9},~{q10},~{q11},~{q12},~{q13},~{q14},~{q15}"() nounwind 80 store double %1, ptr %p, align 4 81 ret void 82} 83