1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=thumbv6m-none-eabi < %s | FileCheck %s --check-prefix=CHECKT1 3; RUN: llc -verify-machineinstrs -mtriple=thumbv7m-none-eabi < %s | FileCheck %s --check-prefixes=CHECKT2 4; RUN: llc -verify-machineinstrs -mtriple=thumbv8.1m.main-none-eabi < %s | FileCheck %s --check-prefixes=CHECKT2 5 6declare i64 @llvm.abs.i64(i64, i1 immarg) 7 8define i64 @neg_abs64(i64 %x) { 9; CHECKT1-LABEL: neg_abs64: 10; CHECKT1: @ %bb.0: 11; CHECKT1-NEXT: asrs r2, r1, #31 12; CHECKT1-NEXT: eors r1, r2 13; CHECKT1-NEXT: eors r0, r2 14; CHECKT1-NEXT: subs r0, r2, r0 15; CHECKT1-NEXT: sbcs r2, r1 16; CHECKT1-NEXT: mov r1, r2 17; CHECKT1-NEXT: bx lr 18; 19; CHECKT2-LABEL: neg_abs64: 20; CHECKT2: @ %bb.0: 21; CHECKT2-NEXT: eor.w r0, r0, r1, asr #31 22; CHECKT2-NEXT: eor.w r2, r1, r1, asr #31 23; CHECKT2-NEXT: asrs r3, r1, #31 24; CHECKT2-NEXT: rsbs r0, r0, r1, asr #31 25; CHECKT2-NEXT: sbc.w r1, r3, r2 26; CHECKT2-NEXT: bx lr 27 %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true) 28 %neg = sub nsw i64 0, %abs 29 ret i64 %neg 30} 31 32declare i32 @llvm.abs.i32(i32, i1 immarg) 33 34define i32 @neg_abs32(i32 %x) { 35; CHECKT1-LABEL: neg_abs32: 36; CHECKT1: @ %bb.0: 37; CHECKT1-NEXT: asrs r1, r0, #31 38; CHECKT1-NEXT: eors r0, r1 39; CHECKT1-NEXT: subs r0, r1, r0 40; CHECKT1-NEXT: bx lr 41; 42; CHECKT2-LABEL: neg_abs32: 43; CHECKT2: @ %bb.0: 44; CHECKT2-NEXT: eor.w r1, r0, r0, asr #31 45; CHECKT2-NEXT: rsb r0, r1, r0, asr #31 46; CHECKT2-NEXT: bx lr 47 %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true) 48 %neg = sub nsw i32 0, %abs 49 ret i32 %neg 50} 51 52declare i16 @llvm.abs.i16(i16, i1 immarg) 53 54define i16 @neg_abs16(i16 %x) { 55; CHECKT1-LABEL: neg_abs16: 56; CHECKT1: @ %bb.0: 57; CHECKT1-NEXT: sxth r1, r0 58; CHECKT1-NEXT: asrs r1, r1, #15 59; CHECKT1-NEXT: eors r0, r1 60; CHECKT1-NEXT: subs r0, r1, r0 61; CHECKT1-NEXT: bx lr 62; 63; CHECKT2-LABEL: neg_abs16: 64; CHECKT2: @ %bb.0: 65; CHECKT2-NEXT: sxth r1, r0 66; CHECKT2-NEXT: eor.w r0, r0, r1, asr #15 67; CHECKT2-NEXT: rsb r0, r0, r1, asr #15 68; CHECKT2-NEXT: bx lr 69 %abs = tail call i16 @llvm.abs.i16(i16 %x, i1 true) 70 %neg = sub nsw i16 0, %abs 71 ret i16 %neg 72} 73 74 75declare i128 @llvm.abs.i128(i128, i1 immarg) 76 77define i128 @neg_abs128(i128 %x) { 78; CHECKT1-LABEL: neg_abs128: 79; CHECKT1: @ %bb.0: 80; CHECKT1-NEXT: .save {r4, r5, r6, lr} 81; CHECKT1-NEXT: push {r4, r5, r6, lr} 82; CHECKT1-NEXT: asrs r4, r3, #31 83; CHECKT1-NEXT: eors r3, r4 84; CHECKT1-NEXT: eors r2, r4 85; CHECKT1-NEXT: eors r1, r4 86; CHECKT1-NEXT: eors r0, r4 87; CHECKT1-NEXT: subs r0, r4, r0 88; CHECKT1-NEXT: mov r5, r4 89; CHECKT1-NEXT: sbcs r5, r1 90; CHECKT1-NEXT: mov r6, r4 91; CHECKT1-NEXT: sbcs r6, r2 92; CHECKT1-NEXT: sbcs r4, r3 93; CHECKT1-NEXT: mov r1, r5 94; CHECKT1-NEXT: mov r2, r6 95; CHECKT1-NEXT: mov r3, r4 96; CHECKT1-NEXT: pop {r4, r5, r6, pc} 97; 98; CHECKT2-LABEL: neg_abs128: 99; CHECKT2: @ %bb.0: 100; CHECKT2-NEXT: .save {r7, lr} 101; CHECKT2-NEXT: push {r7, lr} 102; CHECKT2-NEXT: eor.w r0, r0, r3, asr #31 103; CHECKT2-NEXT: eor.w r1, r1, r3, asr #31 104; CHECKT2-NEXT: eor.w r2, r2, r3, asr #31 105; CHECKT2-NEXT: asr.w lr, r3, #31 106; CHECKT2-NEXT: rsbs r0, r0, r3, asr #31 107; CHECKT2-NEXT: eor.w r12, r3, r3, asr #31 108; CHECKT2-NEXT: sbcs.w r1, lr, r1 109; CHECKT2-NEXT: sbcs.w r2, lr, r2 110; CHECKT2-NEXT: sbc.w r3, lr, r12 111; CHECKT2-NEXT: pop {r7, pc} 112 %abs = tail call i128 @llvm.abs.i128(i128 %x, i1 true) 113 %neg = sub nsw i128 0, %abs 114 ret i128 %neg 115} 116 117 118 119define i64 @abs64(i64 %x) { 120; CHECKT1-LABEL: abs64: 121; CHECKT1: @ %bb.0: 122; CHECKT1-NEXT: asrs r2, r1, #31 123; CHECKT1-NEXT: eors r1, r2 124; CHECKT1-NEXT: eors r0, r2 125; CHECKT1-NEXT: subs r0, r0, r2 126; CHECKT1-NEXT: sbcs r1, r2 127; CHECKT1-NEXT: bx lr 128; 129; CHECKT2-LABEL: abs64: 130; CHECKT2: @ %bb.0: 131; CHECKT2-NEXT: eor.w r0, r0, r1, asr #31 132; CHECKT2-NEXT: eor.w r2, r1, r1, asr #31 133; CHECKT2-NEXT: subs.w r0, r0, r1, asr #31 134; CHECKT2-NEXT: sbc.w r1, r2, r1, asr #31 135; CHECKT2-NEXT: bx lr 136 %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true) 137 ret i64 %abs 138} 139 140define i32 @abs32(i32 %x) { 141; CHECKT1-LABEL: abs32: 142; CHECKT1: @ %bb.0: 143; CHECKT1-NEXT: asrs r1, r0, #31 144; CHECKT1-NEXT: eors r0, r1 145; CHECKT1-NEXT: subs r0, r0, r1 146; CHECKT1-NEXT: bx lr 147; 148; CHECKT2-LABEL: abs32: 149; CHECKT2: @ %bb.0: 150; CHECKT2-NEXT: cmp r0, #0 151; CHECKT2-NEXT: it mi 152; CHECKT2-NEXT: rsbmi r0, r0, #0 153; CHECKT2-NEXT: bx lr 154 %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true) 155 ret i32 %abs 156} 157 158define i16 @abs16(i16 %x) { 159; CHECKT1-LABEL: abs16: 160; CHECKT1: @ %bb.0: 161; CHECKT1-NEXT: sxth r1, r0 162; CHECKT1-NEXT: asrs r1, r1, #15 163; CHECKT1-NEXT: eors r0, r1 164; CHECKT1-NEXT: subs r0, r0, r1 165; CHECKT1-NEXT: bx lr 166; 167; CHECKT2-LABEL: abs16: 168; CHECKT2: @ %bb.0: 169; CHECKT2-NEXT: sxth r1, r0 170; CHECKT2-NEXT: eor.w r0, r0, r1, asr #15 171; CHECKT2-NEXT: sub.w r0, r0, r1, asr #15 172; CHECKT2-NEXT: bx lr 173 %abs = tail call i16 @llvm.abs.i16(i16 %x, i1 true) 174 ret i16 %abs 175} 176 177define i128 @abs128(i128 %x) { 178; CHECKT1-LABEL: abs128: 179; CHECKT1: @ %bb.0: 180; CHECKT1-NEXT: .save {r4, lr} 181; CHECKT1-NEXT: push {r4, lr} 182; CHECKT1-NEXT: asrs r4, r3, #31 183; CHECKT1-NEXT: eors r3, r4 184; CHECKT1-NEXT: eors r2, r4 185; CHECKT1-NEXT: eors r1, r4 186; CHECKT1-NEXT: eors r0, r4 187; CHECKT1-NEXT: subs r0, r0, r4 188; CHECKT1-NEXT: sbcs r1, r4 189; CHECKT1-NEXT: sbcs r2, r4 190; CHECKT1-NEXT: sbcs r3, r4 191; CHECKT1-NEXT: pop {r4, pc} 192; 193; CHECKT2-LABEL: abs128: 194; CHECKT2: @ %bb.0: 195; CHECKT2-NEXT: eor.w r0, r0, r3, asr #31 196; CHECKT2-NEXT: eor.w r1, r1, r3, asr #31 197; CHECKT2-NEXT: subs.w r0, r0, r3, asr #31 198; CHECKT2-NEXT: eor.w r2, r2, r3, asr #31 199; CHECKT2-NEXT: sbcs.w r1, r1, r3, asr #31 200; CHECKT2-NEXT: eor.w r12, r3, r3, asr #31 201; CHECKT2-NEXT: sbcs.w r2, r2, r3, asr #31 202; CHECKT2-NEXT: sbc.w r3, r12, r3, asr #31 203; CHECKT2-NEXT: bx lr 204 %abs = tail call i128 @llvm.abs.i128(i128 %x, i1 true) 205 ret i128 %abs 206} 207 208