1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc -mtriple=thumbv7-apple-darwin %s -o - | FileCheck %s 3 4define i8 @scmp_8_8(i8 signext %x, i8 signext %y) nounwind { 5; CHECK-LABEL: scmp_8_8: 6; CHECK: @ %bb.0: 7; CHECK-NEXT: cmp r0, r1 8; CHECK-NEXT: mov.w r0, #0 9; CHECK-NEXT: mov.w r2, #0 10; CHECK-NEXT: it lt 11; CHECK-NEXT: movlt r0, #1 12; CHECK-NEXT: it gt 13; CHECK-NEXT: movgt r2, #1 14; CHECK-NEXT: subs r0, r2, r0 15; CHECK-NEXT: bx lr 16 %1 = call i8 @llvm.scmp(i8 %x, i8 %y) 17 ret i8 %1 18} 19 20define i8 @scmp_8_16(i16 signext %x, i16 signext %y) nounwind { 21; CHECK-LABEL: scmp_8_16: 22; CHECK: @ %bb.0: 23; CHECK-NEXT: cmp r0, r1 24; CHECK-NEXT: mov.w r0, #0 25; CHECK-NEXT: mov.w r2, #0 26; CHECK-NEXT: it lt 27; CHECK-NEXT: movlt r0, #1 28; CHECK-NEXT: it gt 29; CHECK-NEXT: movgt r2, #1 30; CHECK-NEXT: subs r0, r2, r0 31; CHECK-NEXT: bx lr 32 %1 = call i8 @llvm.scmp(i16 %x, i16 %y) 33 ret i8 %1 34} 35 36define i8 @scmp_8_32(i32 %x, i32 %y) nounwind { 37; CHECK-LABEL: scmp_8_32: 38; CHECK: @ %bb.0: 39; CHECK-NEXT: cmp r0, r1 40; CHECK-NEXT: mov.w r0, #0 41; CHECK-NEXT: mov.w r2, #0 42; CHECK-NEXT: it lt 43; CHECK-NEXT: movlt r0, #1 44; CHECK-NEXT: it gt 45; CHECK-NEXT: movgt r2, #1 46; CHECK-NEXT: subs r0, r2, r0 47; CHECK-NEXT: bx lr 48 %1 = call i8 @llvm.scmp(i32 %x, i32 %y) 49 ret i8 %1 50} 51 52define i8 @scmp_8_64(i64 %x, i64 %y) nounwind { 53; CHECK-LABEL: scmp_8_64: 54; CHECK: @ %bb.0: 55; CHECK-NEXT: subs.w r12, r0, r2 56; CHECK-NEXT: mov.w r9, #0 57; CHECK-NEXT: sbcs.w r12, r1, r3 58; CHECK-NEXT: mov.w r12, #0 59; CHECK-NEXT: it lt 60; CHECK-NEXT: movlt.w r12, #1 61; CHECK-NEXT: subs r0, r2, r0 62; CHECK-NEXT: sbcs.w r0, r3, r1 63; CHECK-NEXT: it lt 64; CHECK-NEXT: movlt.w r9, #1 65; CHECK-NEXT: sub.w r0, r9, r12 66; CHECK-NEXT: bx lr 67 %1 = call i8 @llvm.scmp(i64 %x, i64 %y) 68 ret i8 %1 69} 70 71define i8 @scmp_8_128(i128 %x, i128 %y) nounwind { 72; CHECK-LABEL: scmp_8_128: 73; CHECK: @ %bb.0: 74; CHECK-NEXT: push {r4, r5, r6, lr} 75; CHECK-NEXT: add.w lr, sp, #16 76; CHECK-NEXT: ldr r4, [sp, #28] 77; CHECK-NEXT: movs r5, #0 78; CHECK-NEXT: ldm.w lr, {r9, r12, lr} 79; CHECK-NEXT: subs.w r6, r0, r9 80; CHECK-NEXT: sbcs.w r6, r1, r12 81; CHECK-NEXT: sbcs.w r6, r2, lr 82; CHECK-NEXT: sbcs.w r6, r3, r4 83; CHECK-NEXT: mov.w r6, #0 84; CHECK-NEXT: it lt 85; CHECK-NEXT: movlt r6, #1 86; CHECK-NEXT: subs.w r0, r9, r0 87; CHECK-NEXT: sbcs.w r0, r12, r1 88; CHECK-NEXT: sbcs.w r0, lr, r2 89; CHECK-NEXT: sbcs.w r0, r4, r3 90; CHECK-NEXT: it lt 91; CHECK-NEXT: movlt r5, #1 92; CHECK-NEXT: subs r0, r5, r6 93; CHECK-NEXT: pop {r4, r5, r6, pc} 94 %1 = call i8 @llvm.scmp(i128 %x, i128 %y) 95 ret i8 %1 96} 97 98define i32 @scmp_32_32(i32 %x, i32 %y) nounwind { 99; CHECK-LABEL: scmp_32_32: 100; CHECK: @ %bb.0: 101; CHECK-NEXT: cmp r0, r1 102; CHECK-NEXT: mov.w r0, #0 103; CHECK-NEXT: mov.w r2, #0 104; CHECK-NEXT: it lt 105; CHECK-NEXT: movlt r0, #1 106; CHECK-NEXT: it gt 107; CHECK-NEXT: movgt r2, #1 108; CHECK-NEXT: subs r0, r2, r0 109; CHECK-NEXT: bx lr 110 %1 = call i32 @llvm.scmp(i32 %x, i32 %y) 111 ret i32 %1 112} 113 114define i32 @scmp_32_64(i64 %x, i64 %y) nounwind { 115; CHECK-LABEL: scmp_32_64: 116; CHECK: @ %bb.0: 117; CHECK-NEXT: subs.w r12, r0, r2 118; CHECK-NEXT: mov.w r9, #0 119; CHECK-NEXT: sbcs.w r12, r1, r3 120; CHECK-NEXT: mov.w r12, #0 121; CHECK-NEXT: it lt 122; CHECK-NEXT: movlt.w r12, #1 123; CHECK-NEXT: subs r0, r2, r0 124; CHECK-NEXT: sbcs.w r0, r3, r1 125; CHECK-NEXT: it lt 126; CHECK-NEXT: movlt.w r9, #1 127; CHECK-NEXT: sub.w r0, r9, r12 128; CHECK-NEXT: bx lr 129 %1 = call i32 @llvm.scmp(i64 %x, i64 %y) 130 ret i32 %1 131} 132 133define i64 @scmp_64_64(i64 %x, i64 %y) nounwind { 134; CHECK-LABEL: scmp_64_64: 135; CHECK: @ %bb.0: 136; CHECK-NEXT: subs.w r12, r0, r2 137; CHECK-NEXT: mov.w r9, #0 138; CHECK-NEXT: sbcs.w r12, r1, r3 139; CHECK-NEXT: mov.w r12, #0 140; CHECK-NEXT: it lt 141; CHECK-NEXT: movlt.w r12, #1 142; CHECK-NEXT: subs r0, r2, r0 143; CHECK-NEXT: sbcs.w r0, r3, r1 144; CHECK-NEXT: it lt 145; CHECK-NEXT: movlt.w r9, #1 146; CHECK-NEXT: sub.w r0, r9, r12 147; CHECK-NEXT: asrs r1, r0, #31 148; CHECK-NEXT: bx lr 149 %1 = call i64 @llvm.scmp(i64 %x, i64 %y) 150 ret i64 %1 151} 152