xref: /llvm-project/llvm/test/CodeGen/Thumb/rev.ll (revision 46eef7687639eca1319a93d93d9e588ee0219f8c) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumb-eabi -mattr=+v6 %s -o - | FileCheck %s
3
4define i32 @test1(i32 %X) nounwind {
5; CHECK-LABEL: test1:
6; CHECK:       @ %bb.0:
7; CHECK-NEXT:    rev16 r0, r0
8; CHECK-NEXT:    bx lr
9        %tmp1 = lshr i32 %X, 8
10        %X15 = bitcast i32 %X to i32
11        %tmp4 = shl i32 %X15, 8
12        %tmp2 = and i32 %tmp1, 16711680
13        %tmp5 = and i32 %tmp4, -16777216
14        %tmp9 = and i32 %tmp1, 255
15        %tmp13 = and i32 %tmp4, 65280
16        %tmp6 = or i32 %tmp5, %tmp2
17        %tmp10 = or i32 %tmp6, %tmp13
18        %tmp14 = or i32 %tmp10, %tmp9
19        ret i32 %tmp14
20}
21
22define i32 @test2(i32 %X) nounwind {
23; CHECK-LABEL: test2:
24; CHECK:       @ %bb.0:
25; CHECK-NEXT:    revsh r0, r0
26; CHECK-NEXT:    bx lr
27        %tmp1 = lshr i32 %X, 8
28        %tmp1.upgrd.1 = trunc i32 %tmp1 to i16
29        %tmp3 = trunc i32 %X to i16
30        %tmp2 = and i16 %tmp1.upgrd.1, 255
31        %tmp4 = shl i16 %tmp3, 8
32        %tmp5 = or i16 %tmp2, %tmp4
33        %tmp5.upgrd.2 = sext i16 %tmp5 to i32
34        ret i32 %tmp5.upgrd.2
35}
36
37; rdar://9147637
38define i32 @test3(i16 zeroext %a) nounwind {
39; CHECK-LABEL: test3:
40; CHECK:       @ %bb.0: @ %entry
41; CHECK-NEXT:    revsh r0, r0
42; CHECK-NEXT:    bx lr
43entry:
44  %0 = tail call i16 @llvm.bswap.i16(i16 %a)
45  %1 = sext i16 %0 to i32
46  ret i32 %1
47}
48
49declare i16 @llvm.bswap.i16(i16) nounwind readnone
50
51define i32 @test4(i16 zeroext %a) nounwind {
52; CHECK-LABEL: test4:
53; CHECK:       @ %bb.0: @ %entry
54; CHECK-NEXT:    revsh r0, r0
55; CHECK-NEXT:    bx lr
56entry:
57  %conv = zext i16 %a to i32
58  %shr9 = lshr i16 %a, 8
59  %conv2 = zext i16 %shr9 to i32
60  %shl = shl nuw nsw i32 %conv, 8
61  %or = or i32 %conv2, %shl
62  %sext = shl i32 %or, 16
63  %conv8 = ashr exact i32 %sext, 16
64  ret i32 %conv8
65}
66
67define i32 @pr55484(i32 %0) {
68; CHECK-LABEL: pr55484:
69; CHECK:       @ %bb.0:
70; CHECK-NEXT:    lsls r1, r0, #8
71; CHECK-NEXT:    lsrs r0, r0, #8
72; CHECK-NEXT:    orrs r0, r1
73; CHECK-NEXT:    sxth r0, r0
74; CHECK-NEXT:    bx lr
75  %2 = lshr i32 %0, 8
76  %3 = shl i32 %0, 8
77  %4 = or i32 %2, %3
78  %5 = trunc i32 %4 to i16
79  %6 = sext i16 %5 to i32
80  ret i32 %6
81}
82