xref: /llvm-project/llvm/test/CodeGen/SystemZ/vec-rot-02.ll (revision c61eb440059d6e9c18e6f8404e06bf125aa942c9) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; Test vector rotate left instructions with scalar rotate amount.
3;
4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
5
6declare <16 x i8> @llvm.fshl.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
7declare <8 x i16> @llvm.fshl.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
8declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
9declare <2 x i64> @llvm.fshl.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
10
11; Test a v16i8 rotate left.
12define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val, i32 %scalar) {
13; CHECK-LABEL: f1:
14; CHECK:       # %bb.0:
15; CHECK-NEXT:    verllb %v24, %v26, 0(%r2)
16; CHECK-NEXT:    br %r14
17
18  %scalar_tmp = trunc i32 %scalar to i8
19  %tmp = insertelement <16 x i8> undef, i8 %scalar_tmp, i32 0
20  %amt = shufflevector <16 x i8> %tmp, <16 x i8> undef,
21                       <16 x i32> zeroinitializer
22
23  %inv = sub <16 x i8> <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8,
24                        i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>, %amt
25  %parta = shl <16 x i8> %val, %amt
26  %partb = lshr <16 x i8> %val, %inv
27
28  %rotl = or <16 x i8> %parta, %partb
29
30  ret <16 x i8> %rotl
31}
32
33; Test a v16i8 rotate left (matched from fshl).
34define <16 x i8> @f2(<16 x i8> %dummy, <16 x i8> %val, i32 %scalar) {
35; CHECK-LABEL: f2:
36; CHECK:       # %bb.0:
37; CHECK-NEXT:    verllb %v24, %v26, 0(%r2)
38; CHECK-NEXT:    br %r14
39
40  %scalar_tmp = trunc i32 %scalar to i8
41  %tmp = insertelement <16 x i8> undef, i8 %scalar_tmp, i32 0
42  %amt = shufflevector <16 x i8> %tmp, <16 x i8> undef,
43                       <16 x i32> zeroinitializer
44
45  %rotl = tail call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %val, <16 x i8> %val, <16 x i8> %amt)
46
47  ret <16 x i8> %rotl
48}
49
50; Test a v8i16 rotate left.
51define <8 x i16> @f3(<8 x i16> %dummy, <8 x i16> %val, i32 %scalar) {
52; CHECK-LABEL: f3:
53; CHECK:       # %bb.0:
54; CHECK-NEXT:    verllh %v24, %v26, 0(%r2)
55; CHECK-NEXT:    br %r14
56
57  %scalar_tmp = trunc i32 %scalar to i16
58  %tmp = insertelement <8 x i16> undef, i16 %scalar_tmp, i32 0
59  %amt = shufflevector <8 x i16> %tmp, <8 x i16> undef,
60                       <8 x i32> zeroinitializer
61
62  %inv = sub <8 x i16> <i16 16, i16 16, i16 16, i16 16,
63                        i16 16, i16 16, i16 16, i16 16>, %amt
64  %parta = shl <8 x i16> %val, %amt
65  %partb = lshr <8 x i16> %val, %inv
66
67  %rotl = or <8 x i16> %parta, %partb
68
69  ret <8 x i16> %rotl
70}
71
72; Test a v8i16 rotate left (matched from fshl).
73define <8 x i16> @f4(<8 x i16> %dummy, <8 x i16> %val, i32 %scalar) {
74; CHECK-LABEL: f4:
75; CHECK:       # %bb.0:
76; CHECK-NEXT:    verllh %v24, %v26, 0(%r2)
77; CHECK-NEXT:    br %r14
78
79  %scalar_tmp = trunc i32 %scalar to i16
80  %tmp = insertelement <8 x i16> undef, i16 %scalar_tmp, i32 0
81  %amt = shufflevector <8 x i16> %tmp, <8 x i16> undef,
82                       <8 x i32> zeroinitializer
83
84  %rotl = tail call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %val, <8 x i16> %val, <8 x i16> %amt)
85
86  ret <8 x i16> %rotl
87}
88
89; Test a v4i32 rotate left.
90define <4 x i32> @f5(<4 x i32> %dummy, <4 x i32> %val, i32 %scalar) {
91; CHECK-LABEL: f5:
92; CHECK:       # %bb.0:
93; CHECK-NEXT:    verllf %v24, %v26, 0(%r2)
94; CHECK-NEXT:    br %r14
95
96  %tmp = insertelement <4 x i32> undef, i32 %scalar, i32 0
97  %amt = shufflevector <4 x i32> %tmp, <4 x i32> undef,
98                       <4 x i32> zeroinitializer
99
100  %inv = sub <4 x i32> <i32 32, i32 32, i32 32, i32 32>, %amt
101  %parta = shl <4 x i32> %val, %amt
102  %partb = lshr <4 x i32> %val, %inv
103
104  %rotl = or <4 x i32> %parta, %partb
105
106  ret <4 x i32> %rotl
107}
108
109; Test a v4i32 rotate left (matched from fshl).
110define <4 x i32> @f6(<4 x i32> %dummy, <4 x i32> %val, i32 %scalar) {
111; CHECK-LABEL: f6:
112; CHECK:       # %bb.0:
113; CHECK-NEXT:    verllf %v24, %v26, 0(%r2)
114; CHECK-NEXT:    br %r14
115
116  %tmp = insertelement <4 x i32> undef, i32 %scalar, i32 0
117  %amt = shufflevector <4 x i32> %tmp, <4 x i32> undef,
118                       <4 x i32> zeroinitializer
119
120  %rotl = tail call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %val, <4 x i32> %val, <4 x i32> %amt)
121
122  ret <4 x i32> %rotl
123}
124
125; Test a v2i64 rotate left.
126define <2 x i64> @f7(<2 x i64> %dummy, <2 x i64> %val, i32 %scalar) {
127; CHECK-LABEL: f7:
128; CHECK:       # %bb.0:
129; CHECK-NEXT:    verllg %v24, %v26, 0(%r2)
130; CHECK-NEXT:    br %r14
131
132  %scalar_tmp = zext i32 %scalar to i64
133  %tmp = insertelement <2 x i64> undef, i64 %scalar_tmp, i32 0
134  %amt = shufflevector <2 x i64> %tmp, <2 x i64> undef,
135                       <2 x i32> zeroinitializer
136
137  %inv = sub <2 x i64> <i64 64, i64 64>, %amt
138  %parta = shl <2 x i64> %val, %amt
139  %partb = lshr <2 x i64> %val, %inv
140
141  %rotl = or <2 x i64> %parta, %partb
142
143  ret <2 x i64> %rotl
144}
145
146; Test a v2i64 rotate left (matched from fshl).
147define <2 x i64> @f8(<2 x i64> %dummy, <2 x i64> %val, i32 %scalar) {
148; CHECK-LABEL: f8:
149; CHECK:       # %bb.0:
150; CHECK-NEXT:    verllg %v24, %v26, 0(%r2)
151; CHECK-NEXT:    br %r14
152
153  %scalar_tmp = zext i32 %scalar to i64
154  %tmp = insertelement <2 x i64> undef, i64 %scalar_tmp, i32 0
155  %amt = shufflevector <2 x i64> %tmp, <2 x i64> undef,
156                       <2 x i32> zeroinitializer
157
158  %rotl = tail call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %val, <2 x i64> %val, <2 x i64> %amt)
159
160  ret <2 x i64> %rotl
161}
162
163; Test a v2i64 rotate left (matched from fshl).
164define <2 x i64> @f9(<2 x i64> %dummy, <2 x i64> %val, i64 %scalar) {
165; CHECK-LABEL: f9:
166; CHECK:       # %bb.0:
167; CHECK-NEXT:    verllg %v24, %v26, 0(%r2)
168; CHECK-NEXT:    br %r14
169
170  %tmp = insertelement <2 x i64> undef, i64 %scalar, i32 0
171  %amt = shufflevector <2 x i64> %tmp, <2 x i64> undef,
172                       <2 x i32> zeroinitializer
173
174  %rotl = tail call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %val, <2 x i64> %val, <2 x i64> %amt)
175
176  ret <2 x i64> %rotl
177}
178