xref: /llvm-project/llvm/test/CodeGen/SystemZ/vec-div-03.ll (revision 8424bf207efd89eacf2fe893b67be98d535e1db6) 
1; Test vector division on arch15.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
4
5; Test a v4i32 signed division.
6define <4 x i32> @f1(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
7; CHECK-LABEL: f1:
8; CHECK: vdf %v24, %v26, %v28
9; CHECK: br %r14
10  %ret = sdiv <4 x i32> %val1, %val2
11  ret <4 x i32> %ret
12}
13
14; Test a v4i32 unsigned division.
15define <4 x i32> @f2(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
16; CHECK-LABEL: f2:
17; CHECK: vdlf %v24, %v26, %v28
18; CHECK: br %r14
19  %ret = udiv <4 x i32> %val1, %val2
20  ret <4 x i32> %ret
21}
22
23; Test a v4i32 signed remainder.
24define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
25; CHECK-LABEL: f3:
26; CHECK: vrf %v24, %v26, %v28
27; CHECK: br %r14
28  %ret = srem <4 x i32> %val1, %val2
29  ret <4 x i32> %ret
30}
31
32; Test a v4i32 unsigned remainder.
33define <4 x i32> @f4(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
34; CHECK-LABEL: f4:
35; CHECK: vrlf %v24, %v26, %v28
36; CHECK: br %r14
37  %ret = urem <4 x i32> %val1, %val2
38  ret <4 x i32> %ret
39}
40
41; Test a v2i64 signed division.
42define <2 x i64> @f5(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
43; CHECK-LABEL: f5:
44; CHECK: vdg %v24, %v26, %v28
45; CHECK: br %r14
46  %ret = sdiv <2 x i64> %val1, %val2
47  ret <2 x i64> %ret
48}
49
50; Test a v2i64 unsigned division.
51define <2 x i64> @f6(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
52; CHECK-LABEL: f6:
53; CHECK: vdlg %v24, %v26, %v28
54; CHECK: br %r14
55  %ret = udiv <2 x i64> %val1, %val2
56  ret <2 x i64> %ret
57}
58
59; Test a v2i64 signed remainder.
60define <2 x i64> @f7(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
61; CHECK-LABEL: f7:
62; CHECK: vrg %v24, %v26, %v28
63; CHECK: br %r14
64  %ret = srem <2 x i64> %val1, %val2
65  ret <2 x i64> %ret
66}
67
68; Test a v2i64 unsigned remainder.
69define <2 x i64> @f8(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
70; CHECK-LABEL: f8:
71; CHECK: vrlg %v24, %v26, %v28
72; CHECK: br %r14
73  %ret = urem <2 x i64> %val1, %val2
74  ret <2 x i64> %ret
75}
76
77