xref: /llvm-project/llvm/test/CodeGen/SystemZ/vec-cmp-cmp-logic-select.ll (revision 2f12e45d5ae1adbc2b45f11191d0db6a0f8352b9) 
1; Test that a vector select with a logic combination of two compares do not
2; produce any unnecessary pack, unpack or shift instructions.
3; And, Or and Xor are tested.
4;
5; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
6; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s -check-prefix=CHECK-Z14
7
8define <2 x i8> @fun0(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i8> %val5, <2 x i8> %val6) {
9; CHECK-LABEL: fun0:
10; CHECK:       # %bb.0:
11; CHECK-DAG:     vceqb [[REG0:%v[0-9]+]], %v24, %v26
12; CHECK-DAG:     vceqb [[REG1:%v[0-9]+]], %v28, %v30
13; CHECK-NEXT:    vn %v0, [[REG0]], [[REG1]]
14; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
15; CHECK-NEXT:    br %r14
16  %cmp0 = icmp eq <2 x i8> %val1, %val2
17  %cmp1 = icmp eq <2 x i8> %val3, %val4
18  %and = and <2 x i1> %cmp0, %cmp1
19  %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val6
20  ret <2 x i8> %sel
21}
22
23define <2 x i16> @fun1(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i16> %val5, <2 x i16> %val6) {
24; CHECK-LABEL: fun1:
25; CHECK:       # %bb.0:
26; CHECK-DAG:     vceqb [[REG0:%v[0-9]+]], %v24, %v26
27; CHECK-DAG:     vceqb [[REG1:%v[0-9]+]], %v28, %v30
28; CHECK-NEXT:    vn %v0, [[REG0]], [[REG1]]
29; CHECK-NEXT:    vuphb %v0, %v0
30; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
31; CHECK-NEXT:    br %r14
32  %cmp0 = icmp eq <2 x i8> %val1, %val2
33  %cmp1 = icmp eq <2 x i8> %val3, %val4
34  %and = and <2 x i1> %cmp0, %cmp1
35  %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
36  ret <2 x i16> %sel
37}
38
39define <16 x i8> @fun2(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i8> %val5, <16 x i8> %val6) {
40; CHECK-LABEL: fun2:
41; CHECK:       # %bb.0:
42; CHECK-DAG:     vceqh [[REG0:%v[0-9]+]], %v30, %v27
43; CHECK-DAG:     vceqh [[REG1:%v[0-9]+]], %v28, %v25
44; CHECK-DAG:     vceqb [[REG2:%v[0-9]+]], %v24, %v26
45; CHECK-DAG:     vpkh [[REG3:%v[0-9]+]], [[REG1]], [[REG0]]
46; CHECK-NEXT:    vo %v0, [[REG2]], [[REG3]]
47; CHECK-NEXT:    vsel %v24, %v29, %v31, %v0
48; CHECK-NEXT:    br %r14
49  %cmp0 = icmp eq <16 x i8> %val1, %val2
50  %cmp1 = icmp eq <16 x i16> %val3, %val4
51  %and = or <16 x i1> %cmp0, %cmp1
52  %sel = select <16 x i1> %and, <16 x i8> %val5, <16 x i8> %val6
53  ret <16 x i8> %sel
54}
55
56define <16 x i16> @fun3(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i16> %val5, <16 x i16> %val6) {
57; CHECK-LABEL: fun3:
58; CHECK:       # %bb.0:
59; CHECK-DAG:     vceqb [[REG0:%v[0-9]+]], %v24, %v26
60; CHECK-DAG:     vuphb [[REG2:%v[0-9]+]], [[REG0]]
61; CHECK-DAG:     vmrlg [[REG1:%v[0-9]+]], [[REG0]], [[REG0]]
62; CHECK-DAG:     vuphb [[REG1]], [[REG1]]
63; CHECK-DAG:     vceqh [[REG3:%v[0-9]+]], %v28, %v25
64; CHECK-DAG:     vceqh [[REG4:%v[0-9]+]], %v30, %v27
65; CHECK-DAG:     vl [[REG5:%v[0-9]+]], 176(%r15)
66; CHECK-DAG:     vl [[REG6:%v[0-9]+]], 160(%r15)
67; CHECK-DAG:     vo [[REG7:%v[0-9]+]], %v2, [[REG4]]
68; CHECK-DAG:     vo [[REG8:%v[0-9]+]], [[REG2]], [[REG3]]
69; CHECK-DAG:     vsel %v24, %v29, [[REG6]], [[REG8]]
70; CHECK-DAG:     vsel %v26, %v31, [[REG5]], [[REG7]]
71; CHECK-NEXT:    br %r14
72  %cmp0 = icmp eq <16 x i8> %val1, %val2
73  %cmp1 = icmp eq <16 x i16> %val3, %val4
74  %and = or <16 x i1> %cmp0, %cmp1
75  %sel = select <16 x i1> %and, <16 x i16> %val5, <16 x i16> %val6
76  ret <16 x i16> %sel
77}
78
79define <32 x i8> @fun4(<32 x i8> %val1, <32 x i8> %val2, <32 x i8> %val3, <32 x i8> %val4, <32 x i8> %val5, <32 x i8> %val6) {
80; CHECK-LABEL: fun4:
81; CHECK:       # %bb.0:
82; CHECK-DAG:     vceqb [[REG0:%v[0-9]+]], %v24, %v28
83; CHECK-DAG:     vceqb [[REG1:%v[0-9]+]], %v26, %v30
84; CHECK-DAG:     vceqb [[REG2:%v[0-9]+]], %v25, %v29
85; CHECK-DAG:     vceqb [[REG3:%v[0-9]+]], %v27, %v31
86; CHECK-DAG:     vl [[REG4:%v[0-9]+]], 208(%r15)
87; CHECK-DAG:     vl [[REG5:%v[0-9]+]], 176(%r15)
88; CHECK-DAG:     vl [[REG6:%v[0-9]+]], 192(%r15)
89; CHECK-DAG:     vl [[REG7:%v[0-9]+]], 160(%r15)
90; CHECK-DAG:     vx [[REG8:%v[0-9]+]], [[REG1]], [[REG3]]
91; CHECK-DAG:     vx [[REG9:%v[0-9]+]], [[REG0]], [[REG2]]
92; CHECK-DAG:     vsel %v24, [[REG7]], [[REG6]], [[REG9]]
93; CHECK-DAG:     vsel %v26, [[REG5]], [[REG4]], [[REG8]]
94; CHECK-NEXT:    br %r14
95  %cmp0 = icmp eq <32 x i8> %val1, %val2
96  %cmp1 = icmp eq <32 x i8> %val3, %val4
97  %and = xor <32 x i1> %cmp0, %cmp1
98  %sel = select <32 x i1> %and, <32 x i8> %val5, <32 x i8> %val6
99  ret <32 x i8> %sel
100}
101
102define <2 x i8> @fun5(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i8> %val5, <2 x i8> %val6) {
103; CHECK-LABEL: fun5:
104; CHECK:       # %bb.0:
105; CHECK-DAG:     vceqh [[REG0:%v[0-9]+]], %v24, %v26
106; CHECK-DAG:     vpkh [[REG1:%v[0-9]+]], [[REG0]], [[REG0]]
107; CHECK-DAG:     vceqb [[REG2:%v[0-9]+]], %v28, %v30
108; CHECK-DAG:     vo %v0, [[REG1]], [[REG2]]
109; CHECK-DAG:     vsel %v24, %v25, %v27, %v0
110; CHECK-NEXT:    br %r14
111  %cmp0 = icmp eq <2 x i16> %val1, %val2
112  %cmp1 = icmp eq <2 x i8> %val3, %val4
113  %and = or <2 x i1> %cmp0, %cmp1
114  %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val6
115  ret <2 x i8> %sel
116}
117
118define <2 x i16> @fun6(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i16> %val5, <2 x i16> %val6) {
119; CHECK-LABEL: fun6:
120; CHECK:       # %bb.0:
121; CHECK-NEXT:    vceqb %v1, %v28, %v30
122; CHECK-NEXT:    vceqh %v0, %v24, %v26
123; CHECK-NEXT:    vuphb %v1, %v1
124; CHECK-NEXT:    vo %v0, %v0, %v1
125; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
126; CHECK-NEXT:    br %r14
127  %cmp0 = icmp eq <2 x i16> %val1, %val2
128  %cmp1 = icmp eq <2 x i8> %val3, %val4
129  %and = or <2 x i1> %cmp0, %cmp1
130  %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
131  ret <2 x i16> %sel
132}
133
134define <2 x i32> @fun7(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i32> %val5, <2 x i32> %val6) {
135; CHECK-LABEL: fun7:
136; CHECK:       # %bb.0:
137; CHECK-NEXT:    vceqb %v1, %v28, %v30
138; CHECK-NEXT:    vceqh %v0, %v24, %v26
139; CHECK-NEXT:    vuphb %v1, %v1
140; CHECK-NEXT:    vo %v0, %v0, %v1
141; CHECK-NEXT:    vuphh %v0, %v0
142; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
143; CHECK-NEXT:    br %r14
144  %cmp0 = icmp eq <2 x i16> %val1, %val2
145  %cmp1 = icmp eq <2 x i8> %val3, %val4
146  %and = or <2 x i1> %cmp0, %cmp1
147  %sel = select <2 x i1> %and, <2 x i32> %val5, <2 x i32> %val6
148  ret <2 x i32> %sel
149}
150
151define <8 x i8> @fun8(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4, <8 x i8> %val5, <8 x i8> %val6) {
152; CHECK-LABEL: fun8:
153; CHECK:       # %bb.0:
154; CHECK-DAG:     vceqh [[REG0:%v[0-9]+]], %v24, %v26
155; CHECK-DAG:     vceqh [[REG1:%v[0-9]+]], %v28, %v30
156; CHECK-NEXT:    vx %v0, [[REG0]], [[REG1]]
157; CHECK-NEXT:    vpkh %v0, %v0, %v0
158; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
159; CHECK-NEXT:    br %r14
160  %cmp0 = icmp eq <8 x i16> %val1, %val2
161  %cmp1 = icmp eq <8 x i16> %val3, %val4
162  %and = xor <8 x i1> %cmp0, %cmp1
163  %sel = select <8 x i1> %and, <8 x i8> %val5, <8 x i8> %val6
164  ret <8 x i8> %sel
165}
166
167define <8 x i16> @fun9(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4, <8 x i16> %val5, <8 x i16> %val6) {
168; CHECK-LABEL: fun9:
169; CHECK:       # %bb.0:
170; CHECK-DAG:     vceqh [[REG0:%v[0-9]+]], %v24, %v26
171; CHECK-DAG:     vceqh [[REG1:%v[0-9]+]], %v28, %v30
172; CHECK-NEXT:    vx %v0, [[REG0]], [[REG1]]
173; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
174; CHECK-NEXT:    br %r14
175  %cmp0 = icmp eq <8 x i16> %val1, %val2
176  %cmp1 = icmp eq <8 x i16> %val3, %val4
177  %and = xor <8 x i1> %cmp0, %cmp1
178  %sel = select <8 x i1> %and, <8 x i16> %val5, <8 x i16> %val6
179  ret <8 x i16> %sel
180}
181
182define <8 x i32> @fun10(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4, <8 x i32> %val5, <8 x i32> %val6) {
183; CHECK-LABEL: fun10:
184; CHECK:       # %bb.0:
185; CHECK-DAG:     vceqh [[REG0:%v[0-9]+]], %v24, %v26
186; CHECK-DAG:     vceqh [[REG1:%v[0-9]+]], %v28, %v30
187; CHECK-NEXT:    vx [[REG2:%v[0-9]+]], [[REG0]], [[REG1]]
188; CHECK-DAG:     vuphh [[REG3:%v[0-9]+]], [[REG2]]
189; CHECK-DAG:     vmrlg [[REG4:%v[0-9]+]], [[REG2]], [[REG2]]
190; CHECK-DAG:     vuphh [[REG5:%v[0-9]+]], [[REG4]]
191; CHECK-NEXT:    vsel %v24, %v25, %v29, [[REG3]]
192; CHECK-NEXT:    vsel %v26, %v27, %v31, [[REG5]]
193; CHECK-NEXT:    br %r14
194  %cmp0 = icmp eq <8 x i16> %val1, %val2
195  %cmp1 = icmp eq <8 x i16> %val3, %val4
196  %and = xor <8 x i1> %cmp0, %cmp1
197  %sel = select <8 x i1> %and, <8 x i32> %val5, <8 x i32> %val6
198  ret <8 x i32> %sel
199}
200
201define <16 x i8> @fun11(<16 x i16> %val1, <16 x i16> %val2, <16 x i32> %val3, <16 x i32> %val4, <16 x i8> %val5, <16 x i8> %val6) {
202; CHECK-LABEL: fun11:
203; CHECK:       # %bb.0:
204; CHECK-DAG:     vl [[REG0:%v[0-9]+]], 192(%r15)
205; CHECK-DAG:     vl [[REG1:%v[0-9]+]], 208(%r15)
206; CHECK-DAG:     vl [[REG2:%v[0-9]+]], 160(%r15)
207; CHECK-DAG:     vl [[REG3:%v[0-9]+]], 176(%r15)
208; CHECK-DAG:     vceqf [[REG4:%v[0-9]+]], %v27, [[REG3]]
209; CHECK-DAG:     vceqf [[REG5:%v[0-9]+]], %v25, [[REG2]]
210; CHECK-DAG:     vceqf [[REG6:%v[0-9]+]], %v31, [[REG1]]
211; CHECK-DAG:     vceqf [[REG7:%v[0-9]+]], %v29, [[REG0]]
212; CHECK-DAG:     vceqh [[REG8:%v[0-9]+]], %v24, %v28
213; CHECK-DAG:     vceqh [[REG9:%v[0-9]+]], %v26, %v30
214; CHECK-DAG:     vpkf [[REG10:%v[0-9]+]], [[REG5]], [[REG4]]
215; CHECK-DAG:     vpkf [[REG11:%v[0-9]+]], [[REG7]], [[REG6]]
216; CHECK-DAG:     vn [[REG12:%v[0-9]+]], [[REG9]], [[REG11]]
217; CHECK-DAG:     vn [[REG13:%v[0-9]+]], [[REG8]], [[REG10]]
218; CHECK-DAG:     vl [[REG14:%v[0-9]+]], 240(%r15)
219; CHECK-DAG:     vl [[REG15:%v[0-9]+]], 224(%r15)
220; CHECK-DAG:     vpkh [[REG16:%v[0-9]+]], [[REG13]], [[REG12]]
221; CHECK-NEXT:    vsel %v24, [[REG15]], [[REG14]], [[REG16]]
222; CHECK-NEXT:    br %r14
223  %cmp0 = icmp eq <16 x i16> %val1, %val2
224  %cmp1 = icmp eq <16 x i32> %val3, %val4
225  %and = and <16 x i1> %cmp0, %cmp1
226  %sel = select <16 x i1> %and, <16 x i8> %val5, <16 x i8> %val6
227  ret <16 x i8> %sel
228}
229
230define <16 x i16> @fun12(<16 x i16> %val1, <16 x i16> %val2, <16 x i32> %val3, <16 x i32> %val4, <16 x i16> %val5, <16 x i16> %val6) {
231; CHECK-LABEL: fun12:
232; CHECK:       # %bb.0:
233; CHECK-DAG:     vl [[REG0:%v[0-9]+]], 192(%r15)
234; CHECK-DAG:     vl [[REG1:%v[0-9]+]], 208(%r15)
235; CHECK-DAG:     vl [[REG2:%v[0-9]+]], 160(%r15)
236; CHECK-DAG:     vl [[REG3:%v[0-9]+]], 176(%r15)
237; CHECK-DAG:     vceqf [[REG4:%v[0-9]+]], %v27, [[REG3]]
238; CHECK-DAG:     vceqf [[REG5:%v[0-9]+]], %v25, [[REG2]]
239; CHECK-DAG:     vceqf [[REG6:%v[0-9]+]], %v31, [[REG1]]
240; CHECK-DAG:     vceqf [[REG7:%v[0-9]+]], %v29, [[REG0]]
241; CHECK-DAG:     vceqh [[REG8:%v[0-9]+]], %v24, %v28
242; CHECK-DAG:     vceqh [[REG9:%v[0-9]+]], %v26, %v30
243; CHECK-DAG:     vpkf [[REG10:%v[0-9]+]], [[REG5]], [[REG4]]
244; CHECK-DAG:     vpkf [[REG11:%v[0-9]+]], [[REG7]], [[REG6]]
245; CHECK-DAG:     vl [[REG12:%v[0-9]+]], 272(%r15)
246; CHECK-DAG:     vl [[REG13:%v[0-9]+]], 240(%r15)
247; CHECK-DAG:     vl [[REG14:%v[0-9]+]], 256(%r15)
248; CHECK-DAG:     vl [[REG15:%v[0-9]+]], 224(%r15)
249; CHECK-DAG:     vn [[REG16:%v[0-9]+]], [[REG9]], [[REG11]]
250; CHECK-DAG:     vn [[REG17:%v[0-9]+]], [[REG8]], [[REG10]]
251; CHECK-DAG:     vsel %v24, [[REG15]], [[REG14]], [[REG17]]
252; CHECK-DAG:     vsel %v26, [[REG13]], [[REG12]], [[REG16]]
253; CHECK-NEXT:    br %r14
254  %cmp0 = icmp eq <16 x i16> %val1, %val2
255  %cmp1 = icmp eq <16 x i32> %val3, %val4
256  %and = and <16 x i1> %cmp0, %cmp1
257  %sel = select <16 x i1> %and, <16 x i16> %val5, <16 x i16> %val6
258  ret <16 x i16> %sel
259}
260
261define <2 x i16> @fun13(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i16> %val5, <2 x i16> %val6) {
262; CHECK-LABEL: fun13:
263; CHECK:       # %bb.0:
264; CHECK-NEXT:    vceqg %v1, %v28, %v30
265; CHECK-NEXT:    vceqf %v0, %v24, %v26
266; CHECK-NEXT:    vpkg %v1, %v1, %v1
267; CHECK-NEXT:    vx %v0, %v0, %v1
268; CHECK-NEXT:    vpkf %v0, %v0, %v0
269; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
270; CHECK-NEXT:    br %r14
271  %cmp0 = icmp eq <2 x i32> %val1, %val2
272  %cmp1 = icmp eq <2 x i64> %val3, %val4
273  %and = xor <2 x i1> %cmp0, %cmp1
274  %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
275  ret <2 x i16> %sel
276}
277
278define <2 x i32> @fun14(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i32> %val5, <2 x i32> %val6) {
279; CHECK-LABEL: fun14:
280; CHECK:       # %bb.0:
281; CHECK-NEXT:    vceqg %v1, %v28, %v30
282; CHECK-NEXT:    vceqf %v0, %v24, %v26
283; CHECK-NEXT:    vpkg %v1, %v1, %v1
284; CHECK-NEXT:    vx %v0, %v0, %v1
285; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
286; CHECK-NEXT:    br %r14
287  %cmp0 = icmp eq <2 x i32> %val1, %val2
288  %cmp1 = icmp eq <2 x i64> %val3, %val4
289  %and = xor <2 x i1> %cmp0, %cmp1
290  %sel = select <2 x i1> %and, <2 x i32> %val5, <2 x i32> %val6
291  ret <2 x i32> %sel
292}
293
294define <2 x i64> @fun15(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i64> %val5, <2 x i64> %val6) {
295; CHECK-LABEL: fun15:
296; CHECK:       # %bb.0:
297; CHECK-DAG:     vceqf [[REG0:%v[0-9]+]], %v24, %v26
298; CHECK-DAG:     vuphf [[REG1:%v[0-9]+]], [[REG0]]
299; CHECK-DAG:     vceqg [[REG2:%v[0-9]+]], %v28, %v30
300; CHECK-NEXT:    vx %v0, [[REG1]], [[REG2]]
301; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
302; CHECK-NEXT:    br %r14
303  %cmp0 = icmp eq <2 x i32> %val1, %val2
304  %cmp1 = icmp eq <2 x i64> %val3, %val4
305  %and = xor <2 x i1> %cmp0, %cmp1
306  %sel = select <2 x i1> %and, <2 x i64> %val5, <2 x i64> %val6
307  ret <2 x i64> %sel
308}
309
310define <4 x i16> @fun16(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x i16> %val4, <4 x i16> %val5, <4 x i16> %val6) {
311; CHECK-LABEL: fun16:
312; CHECK:       # %bb.0:
313; CHECK-DAG:     vceqf [[REG0:%v[0-9]+]], %v24, %v26
314; CHECK-DAG:     vpkf [[REG1:%v[0-9]+]], [[REG0]], [[REG0]]
315; CHECK-DAG:     vceqh [[REG2:%v[0-9]+]], %v28, %v30
316; CHECK-NEXT:    vn %v0, [[REG1]], [[REG2]]
317; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
318; CHECK-NEXT:    br %r14
319  %cmp0 = icmp eq <4 x i32> %val1, %val2
320  %cmp1 = icmp eq <4 x i16> %val3, %val4
321  %and = and <4 x i1> %cmp0, %cmp1
322  %sel = select <4 x i1> %and, <4 x i16> %val5, <4 x i16> %val6
323  ret <4 x i16> %sel
324}
325
326define <4 x i32> @fun17(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x i16> %val4, <4 x i32> %val5, <4 x i32> %val6) {
327; CHECK-LABEL: fun17:
328; CHECK:       # %bb.0:
329; CHECK-NEXT:    vceqh %v1, %v28, %v30
330; CHECK-NEXT:    vceqf %v0, %v24, %v26
331; CHECK-NEXT:    vuphh %v1, %v1
332; CHECK-NEXT:    vn %v0, %v0, %v1
333; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
334; CHECK-NEXT:    br %r14
335  %cmp0 = icmp eq <4 x i32> %val1, %val2
336  %cmp1 = icmp eq <4 x i16> %val3, %val4
337  %and = and <4 x i1> %cmp0, %cmp1
338  %sel = select <4 x i1> %and, <4 x i32> %val5, <4 x i32> %val6
339  ret <4 x i32> %sel
340}
341
342define <4 x i64> @fun18(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x i16> %val4, <4 x i64> %val5, <4 x i64> %val6) {
343; CHECK-LABEL: fun18:
344; CHECK:       # %bb.0:
345; CHECK-NEXT:    vceqh %v1, %v28, %v30
346; CHECK-NEXT:    vceqf %v0, %v24, %v26
347; CHECK-NEXT:    vuphh %v1, %v1
348; CHECK-NEXT:    vn %v0, %v0, %v1
349; CHECK-DAG:     vuphf [[REG0:%v[0-9]+]], %v0
350; CHECK-DAG:     vmrlg [[REG1:%v[0-9]+]], %v0, %v0
351; CHECK-DAG:     vuphf [[REG2:%v[0-9]+]], [[REG1]]
352; CHECK-NEXT:    vsel %v24, %v25, %v29, [[REG0]]
353; CHECK-NEXT:    vsel %v26, %v27, %v31, [[REG2]]
354; CHECK-NEXT:    br %r14
355  %cmp0 = icmp eq <4 x i32> %val1, %val2
356  %cmp1 = icmp eq <4 x i16> %val3, %val4
357  %and = and <4 x i1> %cmp0, %cmp1
358  %sel = select <4 x i1> %and, <4 x i64> %val5, <4 x i64> %val6
359  ret <4 x i64> %sel
360}
361
362define <8 x i16> @fun19(<8 x i32> %val1, <8 x i32> %val2, <8 x i32> %val3, <8 x i32> %val4, <8 x i16> %val5, <8 x i16> %val6) {
363; CHECK-LABEL: fun19:
364; CHECK:       # %bb.0:
365; CHECK-DAG:     vceqf [[REG0:%v[0-9]+]], %v24, %v28
366; CHECK-DAG:     vceqf [[REG1:%v[0-9]+]], %v26, %v30
367; CHECK-DAG:     vceqf [[REG2:%v[0-9]+]], %v25, %v29
368; CHECK-DAG:     vceqf [[REG3:%v[0-9]+]], %v27, %v31
369; CHECK-DAG:     vo [[REG4:%v[0-9]+]], [[REG1]], [[REG3]]
370; CHECK-DAG:     vo [[REG5:%v[0-9]+]], [[REG0]], [[REG2]]
371; CHECK-DAG:     vl [[REG6:%v[0-9]+]], 176(%r15)
372; CHECK-DAG:     vl [[REG7:%v[0-9]+]], 160(%r15)
373; CHECK-DAG:     vpkf [[REG8:%v[0-9]+]], [[REG5]], [[REG4]]
374; CHECK-NEXT:    vsel %v24, [[REG7]], [[REG6]], [[REG8]]
375; CHECK-NEXT:    br %r14
376  %cmp0 = icmp eq <8 x i32> %val1, %val2
377  %cmp1 = icmp eq <8 x i32> %val3, %val4
378  %and = or <8 x i1> %cmp0, %cmp1
379  %sel = select <8 x i1> %and, <8 x i16> %val5, <8 x i16> %val6
380  ret <8 x i16> %sel
381}
382
383define <8 x i32> @fun20(<8 x i32> %val1, <8 x i32> %val2, <8 x i32> %val3, <8 x i32> %val4, <8 x i32> %val5, <8 x i32> %val6) {
384; CHECK-LABEL: fun20:
385; CHECK:       # %bb.0:
386; CHECK-DAG:     vceqf [[REG0:%v[0-9]+]], %v24, %v28
387; CHECK-DAG:     vceqf [[REG1:%v[0-9]+]], %v26, %v30
388; CHECK-DAG:     vceqf [[REG2:%v[0-9]+]], %v25, %v29
389; CHECK-DAG:     vceqf [[REG3:%v[0-9]+]], %v27, %v31
390; CHECK-DAG:     vl [[REG4:%v[0-9]+]], 208(%r15)
391; CHECK-DAG:     vl [[REG5:%v[0-9]+]], 176(%r15)
392; CHECK-DAG:     vl [[REG6:%v[0-9]+]], 192(%r15)
393; CHECK-DAG:     vl [[REG7:%v[0-9]+]], 160(%r15)
394; CHECK-DAG:     vo [[REG8:%v[0-9]+]], [[REG1]], [[REG3]]
395; CHECK-DAG:     vo [[REG9:%v[0-9]+]], [[REG0]], [[REG2]]
396; CHECK-DAG:     vsel %v24, [[REG7]], [[REG6]], [[REG9]]
397; CHECK-DAG:     vsel %v26, [[REG5]], [[REG4]], [[REG8]]
398; CHECK-NEXT:    br %r14
399  %cmp0 = icmp eq <8 x i32> %val1, %val2
400  %cmp1 = icmp eq <8 x i32> %val3, %val4
401  %and = or <8 x i1> %cmp0, %cmp1
402  %sel = select <8 x i1> %and, <8 x i32> %val5, <8 x i32> %val6
403  ret <8 x i32> %sel
404}
405
406define <2 x i32> @fun21(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i32> %val5, <2 x i32> %val6) {
407; CHECK-LABEL: fun21:
408; CHECK:       # %bb.0:
409; CHECK-DAG:     vceqg [[REG0:%v[0-9]+]], %v24, %v26
410; CHECK-DAG:     vceqg [[REG1:%v[0-9]+]], %v28, %v30
411; CHECK-NEXT:    vn %v0, [[REG0]], [[REG1]]
412; CHECK-NEXT:    vpkg %v0, %v0, %v0
413; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
414; CHECK-NEXT:    br %r14
415  %cmp0 = icmp eq <2 x i64> %val1, %val2
416  %cmp1 = icmp eq <2 x i64> %val3, %val4
417  %and = and <2 x i1> %cmp0, %cmp1
418  %sel = select <2 x i1> %and, <2 x i32> %val5, <2 x i32> %val6
419  ret <2 x i32> %sel
420}
421
422define <2 x i64> @fun22(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x i64> %val4, <2 x i64> %val5, <2 x i64> %val6) {
423; CHECK-LABEL: fun22:
424; CHECK:       # %bb.0:
425; CHECK-DAG:     vceqg [[REG0:%v[0-9]+]], %v24, %v26
426; CHECK-DAG:     vceqg [[REG1:%v[0-9]+]], %v28, %v30
427; CHECK-NEXT:    vn %v0, [[REG0]], [[REG1]]
428; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
429; CHECK-NEXT:    br %r14
430  %cmp0 = icmp eq <2 x i64> %val1, %val2
431  %cmp1 = icmp eq <2 x i64> %val3, %val4
432  %and = and <2 x i1> %cmp0, %cmp1
433  %sel = select <2 x i1> %and, <2 x i64> %val5, <2 x i64> %val6
434  ret <2 x i64> %sel
435}
436
437define <4 x i32> @fun23(<4 x i64> %val1, <4 x i64> %val2, <4 x i32> %val3, <4 x i32> %val4, <4 x i32> %val5, <4 x i32> %val6) {
438; CHECK-LABEL: fun23:
439; CHECK:       # %bb.0:
440; CHECK-NEXT:    vceqg %v0, %v26, %v30
441; CHECK-NEXT:    vceqg %v1, %v24, %v28
442; CHECK-NEXT:    vpkg %v0, %v1, %v0
443; CHECK-NEXT:    vceqf %v1, %v25, %v27
444; CHECK-NEXT:    vx %v0, %v0, %v1
445; CHECK-NEXT:    vsel %v24, %v29, %v31, %v0
446; CHECK-NEXT:    br %r14
447  %cmp0 = icmp eq <4 x i64> %val1, %val2
448  %cmp1 = icmp eq <4 x i32> %val3, %val4
449  %and = xor <4 x i1> %cmp0, %cmp1
450  %sel = select <4 x i1> %and, <4 x i32> %val5, <4 x i32> %val6
451  ret <4 x i32> %sel
452}
453
454define <4 x i64> @fun24(<4 x i64> %val1, <4 x i64> %val2, <4 x i32> %val3, <4 x i32> %val4, <4 x i64> %val5, <4 x i64> %val6) {
455; CHECK-LABEL: fun24:
456; CHECK:       # %bb.0:
457; CHECK-NEXT:    vceqf [[REG0:%v[0-9]+]], %v25, %v27
458; CHECK-NEXT:    vuphf [[REG1:%v[0-9]+]], [[REG0]]
459; CHECK-NEXT:    vmrlg [[REG2:%v[0-9]+]], [[REG0]], [[REG0]]
460; CHECK-DAG:     vceqg [[REG3:%v[0-9]+]], %v24, %v28
461; CHECK-DAG:     vceqg [[REG4:%v[0-9]+]], %v26, %v30
462; CHECK-DAG:     vuphf [[REG5:%v[0-9]+]], [[REG2]]
463; CHECK-DAG:     vl [[REG6:%v[0-9]+]], 176(%r15)
464; CHECK-DAG:     vl [[REG7:%v[0-9]+]], 160(%r15)
465; CHECK-DAG:     vx [[REG8:%v[0-9]+]], [[REG4]], [[REG5]]
466; CHECK-DAG:     vx [[REG9:%v[0-9]+]], [[REG3]], [[REG1]]
467; CHECK-DAG:     vsel %v24, %v29, [[REG7]], [[REG9]]
468; CHECK-DAG:     vsel %v26, %v31, [[REG6]], [[REG8]]
469; CHECK-NEXT:    br %r14
470  %cmp0 = icmp eq <4 x i64> %val1, %val2
471  %cmp1 = icmp eq <4 x i32> %val3, %val4
472  %and = xor <4 x i1> %cmp0, %cmp1
473  %sel = select <4 x i1> %and, <4 x i64> %val5, <4 x i64> %val6
474  ret <4 x i64> %sel
475}
476
477define <2 x float> @fun25(<2 x float> %val1, <2 x float> %val2, <2 x double> %val3, <2 x double> %val4, <2 x float> %val5, <2 x float> %val6) {
478; CHECK-LABEL: fun25:
479; CHECK:       # %bb.0:
480; CHECK-NEXT:    vmrlf %v0, %v26, %v26
481; CHECK-NEXT:    vmrlf %v1, %v24, %v24
482; CHECK-NEXT:    vldeb %v0, %v0
483; CHECK-NEXT:    vldeb %v1, %v1
484; CHECK-NEXT:    vfchdb %v0, %v1, %v0
485; CHECK-NEXT:    vmrhf %v1, %v26, %v26
486; CHECK-NEXT:    vmrhf %v2, %v24, %v24
487; CHECK-NEXT:    vldeb %v1, %v1
488; CHECK-NEXT:    vldeb %v2, %v2
489; CHECK-NEXT:    vfchdb %v1, %v2, %v1
490; CHECK-NEXT:    vpkg %v0, %v1, %v0
491; CHECK-NEXT:    vfchdb %v1, %v28, %v30
492; CHECK-NEXT:    vpkg %v1, %v1, %v1
493; CHECK-NEXT:    vo %v0, %v0, %v1
494; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
495; CHECK-NEXT:    br %r14
496;
497; CHECK-Z14-LABEL: fun25:
498; CHECK-Z14:       # %bb.0:
499; CHECK-Z14-NEXT:    vfchdb %v1, %v28, %v30
500; CHECK-Z14-NEXT:    vfchsb %v0, %v24, %v26
501; CHECK-Z14-NEXT:    vpkg %v1, %v1, %v1
502; CHECK-Z14-NEXT:    vo %v0, %v0, %v1
503; CHECK-Z14-NEXT:    vsel %v24, %v25, %v27, %v0
504; CHECK-Z14-NEXT:    br %r14
505  %cmp0 = fcmp ogt <2 x float> %val1, %val2
506  %cmp1 = fcmp ogt <2 x double> %val3, %val4
507  %and = or <2 x i1> %cmp0, %cmp1
508  %sel = select <2 x i1> %and, <2 x float> %val5, <2 x float> %val6
509  ret <2 x float> %sel
510}
511
512define <2 x double> @fun26(<2 x float> %val1, <2 x float> %val2, <2 x double> %val3, <2 x double> %val4, <2 x double> %val5, <2 x double> %val6) {
513; CHECK-LABEL: fun26:
514; CHECK:       # %bb.0:
515; CHECK-NEXT:    vmrlf %v0, %v26, %v26
516; CHECK-NEXT:    vmrlf %v1, %v24, %v24
517; CHECK-NEXT:    vldeb %v0, %v0
518; CHECK-NEXT:    vldeb %v1, %v1
519; CHECK-NEXT:    vfchdb %v0, %v1, %v0
520; CHECK-NEXT:    vmrhf %v1, %v26, %v26
521; CHECK-NEXT:    vmrhf %v2, %v24, %v24
522; CHECK-NEXT:    vldeb %v1, %v1
523; CHECK-NEXT:    vldeb %v2, %v2
524; CHECK-NEXT:    vfchdb %v1, %v2, %v1
525; CHECK-NEXT:    vpkg %v0, %v1, %v0
526; CHECK-NEXT:    vuphf %v0, %v0
527; CHECK-NEXT:    vfchdb %v1, %v28, %v30
528; CHECK-NEXT:    vo %v0, %v0, %v1
529; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
530; CHECK-NEXT:    br %r14
531;
532; CHECK-Z14-LABEL: fun26:
533; CHECK-Z14:       # %bb.0:
534; CHECK-Z14-NEXT:    vfchsb %v0, %v24, %v26
535; CHECK-Z14-NEXT:    vuphf %v0, %v0
536; CHECK-Z14-NEXT:    vfchdb %v1, %v28, %v30
537; CHECK-Z14-NEXT:    vo %v0, %v0, %v1
538; CHECK-Z14-NEXT:    vsel %v24, %v25, %v27, %v0
539; CHECK-Z14-NEXT:    br %r14
540  %cmp0 = fcmp ogt <2 x float> %val1, %val2
541  %cmp1 = fcmp ogt <2 x double> %val3, %val4
542  %and = or <2 x i1> %cmp0, %cmp1
543  %sel = select <2 x i1> %and, <2 x double> %val5, <2 x double> %val6
544  ret <2 x double> %sel
545}
546
547; Also check a widening select of a vector of floats
548define <2 x float> @fun27(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x float> %val5, <2 x float> %val6) {
549; CHECK-LABEL: fun27:
550; CHECK:       # %bb.0:
551; CHECK-DAG:     vceqb [[REG0:%v[0-9]+]], %v24, %v26
552; CHECK-DAG:     vceqb [[REG1:%v[0-9]+]], %v28, %v30
553; CHECK-NEXT:    vo %v0, [[REG0]], [[REG1]]
554; CHECK-NEXT:    vuphb %v0, %v0
555; CHECK-NEXT:    vuphh %v0, %v0
556; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
557; CHECK-NEXT:    br %r14
558  %cmp0 = icmp eq <2 x i8> %val1, %val2
559  %cmp1 = icmp eq <2 x i8> %val3, %val4
560  %and = or <2 x i1> %cmp0, %cmp1
561  %sel = select <2 x i1> %and, <2 x float> %val5, <2 x float> %val6
562  ret <2 x float> %sel
563}
564
565define <4 x float> @fun28(<4 x float> %val1, <4 x float> %val2, <4 x float> %val3, <4 x float> %val4, <4 x float> %val5, <4 x float> %val6) {
566; CHECK-LABEL: fun28:
567; CHECK:       # %bb.0:
568; CHECK-DAG:     vmrlf [[REG0:%v[0-9]+]], %v26, %v26
569; CHECK-DAG:     vmrlf [[REG1:%v[0-9]+]], %v24, %v24
570; CHECK-DAG:     vldeb [[REG2:%v[0-9]+]], [[REG0]]
571; CHECK-DAG:     vldeb [[REG3:%v[0-9]+]], [[REG1]]
572; CHECK-DAG:     vfchdb [[REG4:%v[0-9]+]], [[REG3]], [[REG2]]
573; CHECK-DAG:     vmrhf [[REG5:%v[0-9]+]], %v26, %v26
574; CHECK-DAG:     vmrhf [[REG6:%v[0-9]+]], %v24, %v24
575; CHECK-DAG:     vldeb [[REG7:%v[0-9]+]], [[REG5]]
576; CHECK-DAG:     vmrhf [[REG8:%v[0-9]+]], %v28, %v28
577; CHECK-DAG:     vldeb [[REG9:%v[0-9]+]], [[REG6]]
578; CHECK-DAG:     vfchdb [[REG10:%v[0-9]+]], [[REG9]], [[REG7]]
579; CHECK-DAG:     vpkg [[REG11:%v[0-9]+]], [[REG10]], [[REG4]]
580; CHECK-DAG:     vmrlf [[REG12:%v[0-9]+]], %v30, %v30
581; CHECK-DAG:     vmrlf [[REG13:%v[0-9]+]], %v28, %v28
582; CHECK-DAG:     vldeb [[REG14:%v[0-9]+]], [[REG12]]
583; CHECK-DAG:     vldeb [[REG15:%v[0-9]+]], [[REG13]]
584; CHECK-DAG:     vfchdb [[REG16:%v[0-9]+]], [[REG15]], [[REG14]]
585; CHECK-DAG:     vmrhf [[REG17:%v[0-9]+]], %v30, %v30
586; CHECK-DAG:     vldeb [[REG19:%v[0-9]+]], [[REG17]]
587; CHECK-DAG:     vldeb [[REG20:%v[0-9]+]], [[REG8]]
588; CHECK-NEXT:    vfchdb %v2, [[REG20]], [[REG19]]
589; CHECK-NEXT:    vpkg [[REG21:%v[0-9]+]], %v2, [[REG16]]
590; CHECK-NEXT:    vx %v0, [[REG11]], [[REG21]]
591; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
592; CHECK-NEXT:    br %r14
593;
594; CHECK-Z14-LABEL: fun28:
595; CHECK-Z14:       # %bb.0:
596; CHECK-Z14-NEXT:    vfchsb %v0, %v24, %v26
597; CHECK-Z14-NEXT:    vfchsb %v1, %v28, %v30
598; CHECK-Z14-NEXT:    vx %v0, %v0, %v1
599; CHECK-Z14-NEXT:    vsel %v24, %v25, %v27, %v0
600; CHECK-Z14-NEXT:    br %r14
601  %cmp0 = fcmp ogt <4 x float> %val1, %val2
602  %cmp1 = fcmp ogt <4 x float> %val3, %val4
603  %and = xor <4 x i1> %cmp0, %cmp1
604  %sel = select <4 x i1> %and, <4 x float> %val5, <4 x float> %val6
605  ret <4 x float> %sel
606}
607
608define <4 x double> @fun29(<4 x float> %val1, <4 x float> %val2, <4 x float> %val3, <4 x float> %val4, <4 x double> %val5, <4 x double> %val6) {
609; CHECK-LABEL: fun29:
610; CHECK:       # %bb.0:
611; CHECK-NEXT:    vmrlf %v0, %v26, %v26
612; CHECK-NEXT:    vmrlf %v1, %v24, %v24
613; CHECK-NEXT:    vldeb %v0, %v0
614; CHECK-NEXT:    vldeb %v1, %v1
615; CHECK-NEXT:    vfchdb %v0, %v1, %v0
616; CHECK-NEXT:    vmrhf %v1, %v26, %v26
617; CHECK-NEXT:    vmrhf %v2, %v24, %v24
618; CHECK-NEXT:    vldeb %v1, %v1
619; CHECK-NEXT:    vmrhf %v3, %v28, %v28
620; CHECK-NEXT:    vldeb %v2, %v2
621; CHECK-NEXT:    vfchdb %v1, %v2, %v1
622; CHECK-NEXT:    vpkg %v0, %v1, %v0
623; CHECK-NEXT:    vmrlf %v1, %v30, %v30
624; CHECK-NEXT:    vmrlf %v2, %v28, %v28
625; CHECK-NEXT:    vldeb %v1, %v1
626; CHECK-NEXT:    vldeb %v2, %v2
627; CHECK-NEXT:    vfchdb %v1, %v2, %v1
628; CHECK-NEXT:    vmrhf %v2, %v30, %v30
629; CHECK-NEXT:    vldeb %v2, %v2
630; CHECK-NEXT:    vldeb %v3, %v3
631; CHECK-NEXT:    vfchdb %v2, %v3, %v2
632; CHECK-NEXT:    vpkg %v1, %v2, %v1
633; CHECK-NEXT:    vx %v0, %v0, %v1
634; CHECK-NEXT:    vmrlg %v1, %v0, %v0
635; CHECK-NEXT:    vuphf %v1, %v1
636; CHECK-NEXT:    vuphf %v0, %v0
637; CHECK-NEXT:    vsel %v24, %v25, %v29, %v0
638; CHECK-NEXT:    vsel %v26, %v27, %v31, %v1
639; CHECK-NEXT:    br %r14
640;
641; CHECK-Z14-LABEL: fun29:
642; CHECK-Z14:       # %bb.0:
643; CHECK-Z14-NEXT:    vfchsb %v0, %v24, %v26
644; CHECK-Z14-NEXT:    vfchsb %v1, %v28, %v30
645; CHECK-Z14-NEXT:    vx %v0, %v0, %v1
646; CHECK-Z14-NEXT:    vmrlg %v1, %v0, %v0
647; CHECK-Z14-NEXT:    vuphf %v1, %v1
648; CHECK-Z14-NEXT:    vuphf %v0, %v0
649; CHECK-Z14-NEXT:    vsel %v24, %v25, %v29, %v0
650; CHECK-Z14-NEXT:    vsel %v26, %v27, %v31, %v1
651; CHECK-Z14-NEXT:    br %r14
652  %cmp0 = fcmp ogt <4 x float> %val1, %val2
653  %cmp1 = fcmp ogt <4 x float> %val3, %val4
654  %and = xor <4 x i1> %cmp0, %cmp1
655  %sel = select <4 x i1> %and, <4 x double> %val5, <4 x double> %val6
656  ret <4 x double> %sel
657}
658
659define <8 x float> @fun30(<8 x float> %val1, <8 x float> %val2, <8 x double> %val3, <8 x double> %val4, <8 x float> %val5, <8 x float> %val6) {
660; CHECK-LABEL: fun30:
661; CHECK:       # %bb.0:
662; CHECK-NEXT:    vmrlf %v16, %v28, %v28
663; CHECK-NEXT:    vmrlf %v17, %v24, %v24
664; CHECK-NEXT:    vldeb %v16, %v16
665; CHECK-NEXT:    vldeb %v17, %v17
666; CHECK-NEXT:    vfchdb %v16, %v17, %v16
667; CHECK-NEXT:    vmrhf %v17, %v28, %v28
668; CHECK-NEXT:    vmrhf %v18, %v24, %v24
669; CHECK-NEXT:    vldeb %v17, %v17
670; CHECK-NEXT:    vl %v4, 192(%r15)
671; CHECK-NEXT:    vldeb %v18, %v18
672; CHECK-NEXT:    vl %v5, 208(%r15)
673; CHECK-NEXT:    vl %v6, 160(%r15)
674; CHECK-NEXT:    vl %v7, 176(%r15)
675; CHECK-NEXT:    vl %v0, 272(%r15)
676; CHECK-NEXT:    vl %v1, 240(%r15)
677; CHECK-NEXT:    vfchdb %v17, %v18, %v17
678; CHECK-NEXT:    vl %v2, 256(%r15)
679; CHECK-NEXT:    vl %v3, 224(%r15)
680; CHECK-NEXT:    vpkg %v16, %v17, %v16
681; CHECK-NEXT:    vmrlf %v17, %v30, %v30
682; CHECK-NEXT:    vmrlf %v18, %v26, %v26
683; CHECK-NEXT:    vmrhf %v19, %v26, %v26
684; CHECK-NEXT:    vfchdb %v7, %v27, %v7
685; CHECK-NEXT:    vfchdb %v6, %v25, %v6
686; CHECK-NEXT:    vfchdb %v5, %v31, %v5
687; CHECK-NEXT:    vfchdb %v4, %v29, %v4
688; CHECK-NEXT:    vpkg %v6, %v6, %v7
689; CHECK-NEXT:    vpkg %v4, %v4, %v5
690; CHECK-NEXT:    vn %v5, %v16, %v6
691; CHECK-DAG:     vsel %v24, %v3, %v2, %v5
692; CHECK-DAG:     vldeb %v17, %v17
693; CHECK-NEXT:    vldeb %v18, %v18
694; CHECK-NEXT:    vfchdb %v17, %v18, %v17
695; CHECK-NEXT:    vmrhf %v18, %v30, %v30
696; CHECK-NEXT:    vldeb %v18, %v18
697; CHECK-NEXT:    vldeb %v19, %v19
698; CHECK-NEXT:    vfchdb %v18, %v19, %v18
699; CHECK-NEXT:    vpkg %v17, %v18, %v17
700; CHECK-NEXT:    vn %v4, %v17, %v4
701; CHECK-NEXT:    vsel %v26, %v1, %v0, %v4
702; CHECK-NEXT:    br %r14
703;
704; CHECK-Z14-LABEL: fun30:
705; CHECK-Z14:       # %bb.0:
706; CHECK-Z14-NEXT:    vl %v4, 192(%r15)
707; CHECK-Z14-NEXT:    vl %v5, 208(%r15)
708; CHECK-Z14-NEXT:    vl %v6, 160(%r15)
709; CHECK-Z14-NEXT:    vl %v7, 176(%r15)
710; CHECK-Z14-NEXT:    vfchdb %v7, %v27, %v7
711; CHECK-Z14-NEXT:    vfchdb %v6, %v25, %v6
712; CHECK-Z14-NEXT:    vfchdb %v5, %v31, %v5
713; CHECK-Z14-NEXT:    vfchdb %v4, %v29, %v4
714; CHECK-Z14-DAG:     vfchsb %v16, %v24, %v28
715; CHECK-Z14-DAG:     vfchsb %v17, %v26, %v30
716; CHECK-Z14-DAG:     vpkg %v6, %v6, %v7
717; CHECK-Z14-DAG:     vpkg %v4, %v4, %v5
718; CHECK-Z14-DAG:     vl %v0, 272(%r15)
719; CHECK-Z14-DAG:     vl %v1, 240(%r15)
720; CHECK-Z14-DAG:     vl %v2, 256(%r15)
721; CHECK-Z14-DAG:     vl %v3, 224(%r15)
722; CHECK-Z14-NEXT:    vn %v4, %v17, %v4
723; CHECK-Z14-NEXT:    vn %v5, %v16, %v6
724; CHECK-Z14-NEXT:    vsel %v24, %v3, %v2, %v5
725; CHECK-Z14-NEXT:    vsel %v26, %v1, %v0, %v4
726; CHECK-Z14-NEXT:    br %r14
727  %cmp0 = fcmp ogt <8 x float> %val1, %val2
728  %cmp1 = fcmp ogt <8 x double> %val3, %val4
729  %and = and <8 x i1> %cmp0, %cmp1
730  %sel = select <8 x i1> %and, <8 x float> %val5, <8 x float> %val6
731  ret <8 x float> %sel
732}
733
734define <2 x float> @fun31(<2 x double> %val1, <2 x double> %val2, <2 x double> %val3, <2 x double> %val4, <2 x float> %val5, <2 x float> %val6) {
735; CHECK-LABEL: fun31:
736; CHECK:       # %bb.0:
737; CHECK-DAG:     vfchdb [[REG0:%v[0-9]+]], %v24, %v26
738; CHECK-DAG:     vfchdb [[REG1:%v[0-9]+]], %v28, %v30
739; CHECK-NEXT:    vx %v0, [[REG0]], [[REG1]]
740; CHECK-NEXT:    vpkg %v0, %v0, %v0
741; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
742; CHECK-NEXT:    br %r14
743  %cmp0 = fcmp ogt <2 x double> %val1, %val2
744  %cmp1 = fcmp ogt <2 x double> %val3, %val4
745  %and = xor <2 x i1> %cmp0, %cmp1
746  %sel = select <2 x i1> %and, <2 x float> %val5, <2 x float> %val6
747  ret <2 x float> %sel
748}
749
750define <2 x double> @fun32(<2 x double> %val1, <2 x double> %val2, <2 x double> %val3, <2 x double> %val4, <2 x double> %val5, <2 x double> %val6) {
751; CHECK-LABEL: fun32:
752; CHECK:       # %bb.0:
753; CHECK-DAG:     vfchdb [[REG0:%v[0-9]+]], %v24, %v26
754; CHECK-DAG:     vfchdb [[REG1:%v[0-9]+]], %v28, %v30
755; CHECK-NEXT:    vx %v0, [[REG0]], [[REG1]]
756; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
757; CHECK-NEXT:    br %r14
758  %cmp0 = fcmp ogt <2 x double> %val1, %val2
759  %cmp1 = fcmp ogt <2 x double> %val3, %val4
760  %and = xor <2 x i1> %cmp0, %cmp1
761  %sel = select <2 x i1> %and, <2 x double> %val5, <2 x double> %val6
762  ret <2 x double> %sel
763}
764
765define <4 x float> @fun33(<4 x double> %val1, <4 x double> %val2, <4 x float> %val3, <4 x float> %val4, <4 x float> %val5, <4 x float> %val6) {
766; CHECK-LABEL: fun33:
767; CHECK:       # %bb.0:
768; CHECK-NEXT:    vfchdb %v0, %v26, %v30
769; CHECK-NEXT:    vfchdb %v1, %v24, %v28
770; CHECK-NEXT:    vpkg %v0, %v1, %v0
771; CHECK-NEXT:    vmrlf %v1, %v27, %v27
772; CHECK-NEXT:    vmrlf %v2, %v25, %v25
773; CHECK-NEXT:    vldeb %v1, %v1
774; CHECK-NEXT:    vldeb %v2, %v2
775; CHECK-NEXT:    vfchdb %v1, %v2, %v1
776; CHECK-NEXT:    vmrhf %v2, %v27, %v27
777; CHECK-NEXT:    vmrhf %v3, %v25, %v25
778; CHECK-NEXT:    vldeb %v2, %v2
779; CHECK-NEXT:    vldeb %v3, %v3
780; CHECK-NEXT:    vfchdb %v2, %v3, %v2
781; CHECK-NEXT:    vpkg %v1, %v2, %v1
782; CHECK-NEXT:    vn %v0, %v0, %v1
783; CHECK-NEXT:    vsel %v24, %v29, %v31, %v0
784; CHECK-NEXT:    br %r14
785;
786; CHECK-Z14-LABEL: fun33:
787; CHECK-Z14:       # %bb.0:
788; CHECK-Z14-NEXT:    vfchdb %v0, %v26, %v30
789; CHECK-Z14-NEXT:    vfchdb %v1, %v24, %v28
790; CHECK-Z14-NEXT:    vpkg %v0, %v1, %v0
791; CHECK-Z14-NEXT:    vfchsb %v1, %v25, %v27
792; CHECK-Z14-NEXT:    vn %v0, %v0, %v1
793; CHECK-Z14-NEXT:    vsel %v24, %v29, %v31, %v0
794; CHECK-Z14-NEXT:    br %r14
795  %cmp0 = fcmp ogt <4 x double> %val1, %val2
796  %cmp1 = fcmp ogt <4 x float> %val3, %val4
797  %and = and <4 x i1> %cmp0, %cmp1
798  %sel = select <4 x i1> %and, <4 x float> %val5, <4 x float> %val6
799  ret <4 x float> %sel
800}
801
802define <4 x double> @fun34(<4 x double> %val1, <4 x double> %val2, <4 x float> %val3, <4 x float> %val4, <4 x double> %val5, <4 x double> %val6) {
803; CHECK-LABEL: fun34:
804; CHECK:       # %bb.0:
805; CHECK-NEXT:    vmrlf [[REG0:%v[0-9]+]], %v27, %v27
806; CHECK-NEXT:    vmrlf [[REG1:%v[0-9]+]], %v25, %v25
807; CHECK-NEXT:    vldeb [[REG2:%v[0-9]+]], [[REG0]]
808; CHECK-NEXT:    vldeb [[REG3:%v[0-9]+]], [[REG1]]
809; CHECK-NEXT:    vfchdb [[REG4:%v[0-9]+]], [[REG3]], [[REG2]]
810; CHECK-NEXT:    vmrhf [[REG5:%v[0-9]+]], %v27, %v27
811; CHECK-NEXT:    vmrhf [[REG6:%v[0-9]+]], %v25, %v25
812; CHECK-DAG:     vldeb [[REG7:%v[0-9]+]], [[REG5]]
813; CHECK-DAG:     vl [[REG8:%v[0-9]+]], 176(%r15)
814; CHECK-DAG:     vldeb [[REG9:%v[0-9]+]], [[REG6]]
815; CHECK-DAG:     vl [[REG10:%v[0-9]+]], 160(%r15)
816; CHECK-DAG:     vfchdb [[REG11:%v[0-9]+]], [[REG9]], [[REG7]]
817; CHECK-DAG:     vpkg [[REG12:%v[0-9]+]], [[REG11]], [[REG4]]
818; CHECK-DAG:     vuphf [[REG13:%v[0-9]+]], [[REG12]]
819; CHECK-DAG:     vmrlg [[REG14:%v[0-9]+]], [[REG12]], [[REG12]]
820; CHECK-NEXT:    vfchdb [[REG15:%v[0-9]+]], %v24, %v28
821; CHECK-NEXT:    vfchdb [[REG16:%v[0-9]+]], %v26, %v30
822; CHECK-NEXT:    vuphf [[REG17:%v[0-9]+]], [[REG14]]
823; CHECK-NEXT:    vn [[REG18:%v[0-9]+]], [[REG16]], [[REG17]]
824; CHECK-NEXT:    vn [[REG19:%v[0-9]+]], [[REG15]], [[REG13]]
825; CHECK-NEXT:    vsel %v24, %v29, [[REG10]], [[REG19]]
826; CHECK-NEXT:    vsel %v26, %v31, [[REG8]], [[REG18]]
827; CHECK-NEXT:    br %r14
828;
829; CHECK-Z14-LABEL: fun34:
830; CHECK-Z14:       # %bb.0:
831; CHECK-Z14-NEXT:    vfchsb %v4, %v25, %v27
832; CHECK-Z14-NEXT:    vuphf %v5, %v4
833; CHECK-Z14-NEXT:    vmrlg %v4, %v4, %v4
834; CHECK-Z14-DAG:     vfchdb %v2, %v24, %v28
835; CHECK-Z14-DAG:     vfchdb %v3, %v26, %v30
836; CHECK-Z14-DAG:     vuphf %v4, %v4
837; CHECK-Z14-DAG:     vl %v0, 176(%r15)
838; CHECK-Z14-DAG:     vl %v1, 160(%r15)
839; CHECK-Z14-NEXT:    vn %v3, %v3, %v4
840; CHECK-Z14-NEXT:    vn %v2, %v2, %v5
841; CHECK-Z14-NEXT:    vsel %v24, %v29, %v1, %v2
842; CHECK-Z14-NEXT:    vsel %v26, %v31, %v0, %v3
843; CHECK-Z14-NEXT:    br %r14
844  %cmp0 = fcmp ogt <4 x double> %val1, %val2
845  %cmp1 = fcmp ogt <4 x float> %val3, %val4
846  %and = and <4 x i1> %cmp0, %cmp1
847  %sel = select <4 x i1> %and, <4 x double> %val5, <4 x double> %val6
848  ret <4 x double> %sel
849}
850