xref: /llvm-project/llvm/test/CodeGen/SystemZ/vec-cmp-09.ll (revision 8424bf207efd89eacf2fe893b67be98d535e1db6) 
1; Test usage of VBLEND on arch15.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
4
5define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3) {
6; CHECK-LABEL: f1:
7; CHECK: vblendb %v24, %v26, %v28, %v24
8; CHECK-NEXT: br %r14
9  %cmp = icmp slt <16 x i8> %val1, zeroinitializer
10  %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val3
11  ret <16 x i8> %ret
12}
13
14define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3) {
15; CHECK-LABEL: f2:
16; CHECK: vblendb %v24, %v28, %v26, %v24
17; CHECK-NEXT: br %r14
18  %cmp = icmp sge <16 x i8> %val1, zeroinitializer
19  %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val3
20  ret <16 x i8> %ret
21}
22
23define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3) {
24; CHECK-LABEL: f3:
25; CHECK: vblendb %v24, %v26, %v28, %v24
26; CHECK-NEXT: br %r14
27  %mask = and <16 x i8> %val1, <i8 128, i8 128, i8 128, i8 128,
28                                i8 128, i8 128, i8 128, i8 128,
29                                i8 128, i8 128, i8 128, i8 128,
30                                i8 128, i8 128, i8 128, i8 128>;
31  %cmp = icmp ne <16 x i8> %mask, zeroinitializer
32  %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val3
33  ret <16 x i8> %ret
34}
35
36define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3) {
37; CHECK-LABEL: f4:
38; CHECK: vblendb %v24, %v28, %v26, %v24
39; CHECK-NEXT: br %r14
40  %mask = and <16 x i8> %val1, <i8 128, i8 128, i8 128, i8 128,
41                                i8 128, i8 128, i8 128, i8 128,
42                                i8 128, i8 128, i8 128, i8 128,
43                                i8 128, i8 128, i8 128, i8 128>;
44  %cmp = icmp eq <16 x i8> %mask, zeroinitializer
45  %ret = select <16 x i1> %cmp, <16 x i8> %val2, <16 x i8> %val3
46  ret <16 x i8> %ret
47}
48
49define <8 x i16> @f5(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3) {
50; CHECK-LABEL: f5:
51; CHECK: vblendh %v24, %v26, %v28, %v24
52; CHECK-NEXT: br %r14
53  %cmp = icmp slt <8 x i16> %val1, zeroinitializer
54  %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val3
55  ret <8 x i16> %ret
56}
57
58define <8 x i16> @f6(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3) {
59; CHECK-LABEL: f6:
60; CHECK: vblendh %v24, %v28, %v26, %v24
61; CHECK-NEXT: br %r14
62  %cmp = icmp sge <8 x i16> %val1, zeroinitializer
63  %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val3
64  ret <8 x i16> %ret
65}
66
67define <8 x i16> @f7(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3) {
68; CHECK-LABEL: f7:
69; CHECK: vblendh %v24, %v26, %v28, %v24
70; CHECK-NEXT: br %r14
71  %mask = and <8 x i16> %val1, <i16 32768, i16 32768, i16 32768, i16 32768,
72                                i16 32768, i16 32768, i16 32768, i16 32768>;
73  %cmp = icmp ne <8 x i16> %mask, zeroinitializer
74  %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val3
75  ret <8 x i16> %ret
76}
77
78define <8 x i16> @f8(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3) {
79; CHECK-LABEL: f8:
80; CHECK: vblendh %v24, %v28, %v26, %v24
81; CHECK-NEXT: br %r14
82  %mask = and <8 x i16> %val1, <i16 32768, i16 32768, i16 32768, i16 32768,
83                                i16 32768, i16 32768, i16 32768, i16 32768>;
84  %cmp = icmp eq <8 x i16> %mask, zeroinitializer
85  %ret = select <8 x i1> %cmp, <8 x i16> %val2, <8 x i16> %val3
86  ret <8 x i16> %ret
87}
88
89define <4 x i32> @f9(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3) {
90; CHECK-LABEL: f9:
91; CHECK: vblendf %v24, %v26, %v28, %v24
92; CHECK-NEXT: br %r14
93  %cmp = icmp slt <4 x i32> %val1, zeroinitializer
94  %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val3
95  ret <4 x i32> %ret
96}
97
98define <4 x i32> @f10(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3) {
99; CHECK-LABEL: f10:
100; CHECK: vblendf %v24, %v28, %v26, %v24
101; CHECK-NEXT: br %r14
102  %cmp = icmp sge <4 x i32> %val1, zeroinitializer
103  %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val3
104  ret <4 x i32> %ret
105}
106
107define <4 x i32> @f11(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3) {
108; CHECK-LABEL: f11:
109; CHECK: vblendf %v24, %v26, %v28, %v24
110; CHECK-NEXT: br %r14
111  %mask = and <4 x i32> %val1, <i32 2147483648, i32 2147483648,
112                                i32 2147483648, i32 2147483648>;
113  %cmp = icmp ne <4 x i32> %mask, zeroinitializer
114  %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val3
115  ret <4 x i32> %ret
116}
117
118define <4 x i32> @f12(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3) {
119; CHECK-LABEL: f12:
120; CHECK: vblendf %v24, %v28, %v26, %v24
121; CHECK-NEXT: br %r14
122  %mask = and <4 x i32> %val1, <i32 2147483648, i32 2147483648,
123                                i32 2147483648, i32 2147483648>;
124  %cmp = icmp eq <4 x i32> %mask, zeroinitializer
125  %ret = select <4 x i1> %cmp, <4 x i32> %val2, <4 x i32> %val3
126  ret <4 x i32> %ret
127}
128
129define <2 x i64> @f13(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3) {
130; CHECK-LABEL: f13:
131; CHECK: vblendg %v24, %v26, %v28, %v24
132; CHECK-NEXT: br %r14
133  %cmp = icmp slt <2 x i64> %val1, zeroinitializer
134  %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val3
135  ret <2 x i64> %ret
136}
137
138define <2 x i64> @f14(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3) {
139; CHECK-LABEL: f14:
140; CHECK: vblendg %v24, %v28, %v26, %v24
141; CHECK-NEXT: br %r14
142  %cmp = icmp sge <2 x i64> %val1, zeroinitializer
143  %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val3
144  ret <2 x i64> %ret
145}
146
147define <2 x i64> @f15(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3) {
148; CHECK-LABEL: f15:
149; CHECK: vblendg %v24, %v26, %v28, %v24
150; CHECK-NEXT: br %r14
151  %mask = and <2 x i64> %val1, <i64 9223372036854775808,
152                                i64 9223372036854775808>;
153  %cmp = icmp ne <2 x i64> %mask, zeroinitializer
154  %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val3
155  ret <2 x i64> %ret
156}
157
158define <2 x i64> @f16(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3) {
159; CHECK-LABEL: f16:
160; CHECK: vblendg %v24, %v28, %v26, %v24
161; CHECK-NEXT: br %r14
162  %mask = and <2 x i64> %val1, <i64 9223372036854775808,
163                                i64 9223372036854775808>;
164  %cmp = icmp eq <2 x i64> %mask, zeroinitializer
165  %ret = select <2 x i1> %cmp, <2 x i64> %val2, <2 x i64> %val3
166  ret <2 x i64> %ret
167}
168
169define <4 x float> @f17(<4 x i32> %val1, <4 x float> %val2, <4 x float> %val3) {
170; CHECK-LABEL: f17:
171; CHECK: vblendf %v24, %v26, %v28, %v24
172; CHECK-NEXT: br %r14
173  %cmp = icmp slt <4 x i32> %val1, zeroinitializer
174  %ret = select <4 x i1> %cmp, <4 x float> %val2, <4 x float> %val3
175  ret <4 x float> %ret
176}
177
178define <4 x float> @f18(<4 x i32> %val1, <4 x float> %val2, <4 x float> %val3) {
179; CHECK-LABEL: f18:
180; CHECK: vblendf %v24, %v28, %v26, %v24
181; CHECK-NEXT: br %r14
182  %cmp = icmp sge <4 x i32> %val1, zeroinitializer
183  %ret = select <4 x i1> %cmp, <4 x float> %val2, <4 x float> %val3
184  ret <4 x float> %ret
185}
186
187define <4 x float> @f19(<4 x i32> %val1, <4 x float> %val2, <4 x float> %val3) {
188; CHECK-LABEL: f19:
189; CHECK: vblendf %v24, %v26, %v28, %v24
190; CHECK-NEXT: br %r14
191  %mask = and <4 x i32> %val1, <i32 2147483648, i32 2147483648,
192                                i32 2147483648, i32 2147483648>;
193  %cmp = icmp ne <4 x i32> %mask, zeroinitializer
194  %ret = select <4 x i1> %cmp, <4 x float> %val2, <4 x float> %val3
195  ret <4 x float> %ret
196}
197
198define <4 x float> @f20(<4 x i32> %val1, <4 x float> %val2, <4 x float> %val3) {
199; CHECK-LABEL: f20:
200; CHECK: vblendf %v24, %v28, %v26, %v24
201; CHECK-NEXT: br %r14
202  %mask = and <4 x i32> %val1, <i32 2147483648, i32 2147483648,
203                                i32 2147483648, i32 2147483648>;
204  %cmp = icmp eq <4 x i32> %mask, zeroinitializer
205  %ret = select <4 x i1> %cmp, <4 x float> %val2, <4 x float> %val3
206  ret <4 x float> %ret
207}
208
209define <2 x double> @f21(<2 x i64> %val1, <2 x double> %val2, <2 x double> %val3) {
210; CHECK-LABEL: f21:
211; CHECK: vblendg %v24, %v26, %v28, %v24
212; CHECK-NEXT: br %r14
213  %cmp = icmp slt <2 x i64> %val1, zeroinitializer
214  %ret = select <2 x i1> %cmp, <2 x double> %val2, <2 x double> %val3
215  ret <2 x double> %ret
216}
217
218define <2 x double> @f22(<2 x i64> %val1, <2 x double> %val2, <2 x double> %val3) {
219; CHECK-LABEL: f22:
220; CHECK: vblendg %v24, %v28, %v26, %v24
221; CHECK-NEXT: br %r14
222  %cmp = icmp sge <2 x i64> %val1, zeroinitializer
223  %ret = select <2 x i1> %cmp, <2 x double> %val2, <2 x double> %val3
224  ret <2 x double> %ret
225}
226
227define <2 x double> @f23(<2 x i64> %val1, <2 x double> %val2, <2 x double> %val3) {
228; CHECK-LABEL: f23:
229; CHECK: vblendg %v24, %v26, %v28, %v24
230; CHECK-NEXT: br %r14
231  %mask = and <2 x i64> %val1, <i64 9223372036854775808,
232                                i64 9223372036854775808>;
233  %cmp = icmp ne <2 x i64> %mask, zeroinitializer
234  %ret = select <2 x i1> %cmp, <2 x double> %val2, <2 x double> %val3
235  ret <2 x double> %ret
236}
237
238define <2 x double> @f24(<2 x i64> %val1, <2 x double> %val2, <2 x double> %val3) {
239; CHECK-LABEL: f24:
240; CHECK: vblendg %v24, %v28, %v26, %v24
241; CHECK-NEXT: br %r14
242  %mask = and <2 x i64> %val1, <i64 9223372036854775808,
243                                i64 9223372036854775808>;
244  %cmp = icmp eq <2 x i64> %mask, zeroinitializer
245  %ret = select <2 x i1> %cmp, <2 x double> %val2, <2 x double> %val3
246  ret <2 x double> %ret
247}
248
249