xref: /llvm-project/llvm/test/CodeGen/SystemZ/vec-args-05.ll (revision 0a76f7d9d8c1fc693568ed26420c47d92a6ba0e7)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; Test the handling of unnamed short vector arguments.
3;
4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
5; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-STACK
6
7; This routine is called with two named vector argument (passed
8; in %v24 and %v26) and two unnamed vector arguments (passed
9; in the single-wide stack slots at 160 and 168).
10declare void @bar(<4 x i8>, <4 x i8>, ...)
11
12define void @foo() {
13; CHECK-VEC-LABEL: foo:
14; CHECK-VEC:       # %bb.0:
15; CHECK-VEC-NEXT:    stmg %r14, %r15, 112(%r15)
16; CHECK-VEC-NEXT:    .cfi_offset %r14, -48
17; CHECK-VEC-NEXT:    .cfi_offset %r15, -40
18; CHECK-VEC-NEXT:    aghi %r15, -176
19; CHECK-VEC-NEXT:    .cfi_def_cfa_offset 336
20; CHECK-VEC-NEXT:    larl %r1, .LCPI0_0
21; CHECK-VEC-NEXT:    vl %v0, 0(%r1), 3
22; CHECK-VEC-NEXT:    vrepib %v24, 1
23; CHECK-VEC-NEXT:    vrepib %v26, 2
24; CHECK-VEC-NEXT:    vst %v0, 160(%r15), 3
25; CHECK-VEC-NEXT:    brasl %r14, bar@PLT
26; CHECK-VEC-NEXT:    lmg %r14, %r15, 288(%r15)
27; CHECK-VEC-NEXT:    br %r14
28;
29; CHECK-STACK-LABEL: foo:
30; CHECK-STACK:       # %bb.0:
31; CHECK-STACK-NEXT:    stmg %r14, %r15, 112(%r15)
32; CHECK-STACK-NEXT:    .cfi_offset %r14, -48
33; CHECK-STACK-NEXT:    .cfi_offset %r15, -40
34; CHECK-STACK-NEXT:    aghi %r15, -176
35; CHECK-STACK-NEXT:    .cfi_def_cfa_offset 336
36; CHECK-STACK-NEXT:    larl %r1, .LCPI0_0
37; CHECK-STACK-NEXT:    vl %v0, 0(%r1), 3
38; CHECK-STACK-NEXT:    vrepib %v24, 1
39; CHECK-STACK-NEXT:    vrepib %v26, 2
40; CHECK-STACK-NEXT:    vst %v0, 160(%r15), 3
41; CHECK-STACK-NEXT:    brasl %r14, bar@PLT
42; CHECK-STACK-NEXT:    lmg %r14, %r15, 288(%r15)
43; CHECK-STACK-NEXT:    br %r14
44
45  call void (<4 x i8>, <4 x i8>, ...) @bar
46              (<4 x i8> <i8 1, i8 1, i8 1, i8 1>,
47               <4 x i8> <i8 2, i8 2, i8 2, i8 2>,
48               <4 x i8> <i8 3, i8 3, i8 3, i8 3>,
49               <4 x i8> <i8 4, i8 4, i8 4, i8 4>)
50  ret void
51}
52
53