xref: /llvm-project/llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll (revision a65ccc1b9fe740c9f65d9cf2b627de50278aad56) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 < %s  | FileCheck %s
3
4; Store a <4 x i31> vector.
5define void @fun0(<4 x i31> %src, ptr %p)
6; CHECK-LABEL: fun0:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vlgvf %r0, %v24, 0
9; CHECK-NEXT:    vlvgp %v0, %r0, %r0
10; CHECK-NEXT:    vrepib %v1, 93
11; CHECK-NEXT:    vlgvf %r0, %v24, 1
12; CHECK-NEXT:    vslb %v0, %v0, %v1
13; CHECK-NEXT:    larl %r1, .LCPI0_0
14; CHECK-NEXT:    vl %v2, 0(%r1), 3
15; CHECK-NEXT:    vsl %v0, %v0, %v1
16; CHECK-NEXT:    vlvgp %v1, %r0, %r0
17; CHECK-NEXT:    vn %v1, %v1, %v2
18; CHECK-NEXT:    vrepib %v3, 62
19; CHECK-NEXT:    vslb %v1, %v1, %v3
20; CHECK-NEXT:    vlgvf %r0, %v24, 2
21; CHECK-NEXT:    vsl %v1, %v1, %v3
22; CHECK-NEXT:    vo %v0, %v0, %v1
23; CHECK-NEXT:    vlvgp %v1, %r0, %r0
24; CHECK-NEXT:    vn %v1, %v1, %v2
25; CHECK-NEXT:    vrepib %v3, 31
26; CHECK-NEXT:    vslb %v1, %v1, %v3
27; CHECK-NEXT:    vlgvf %r0, %v24, 3
28; CHECK-NEXT:    vsl %v1, %v1, %v3
29; CHECK-NEXT:    vo %v0, %v0, %v1
30; CHECK-NEXT:    vlvgp %v1, %r0, %r0
31; CHECK-NEXT:    larl %r1, .LCPI0_1
32; CHECK-NEXT:    vn %v1, %v1, %v2
33; CHECK-NEXT:    vo %v0, %v0, %v1
34; CHECK-NEXT:    vl %v1, 0(%r1), 3
35; CHECK-NEXT:    vn %v0, %v0, %v1
36; CHECK-NEXT:    vst %v0, 0(%r2), 4
37; CHECK-NEXT:    br %r14
38{
39  store <4 x i31> %src, ptr %p
40  ret void
41}
42
43; Store a <16 x i1> vector.
44define i16 @fun1(<16 x i1> %src)
45; CHECK-LABEL: fun1:
46; CHECK:       # %bb.0:
47; CHECK-NEXT:    aghi %r15, -168
48; CHECK-NEXT:    .cfi_def_cfa_offset 328
49; CHECK-NEXT:    vlgvb %r0, %v24, 0
50; CHECK-NEXT:    vlgvb %r1, %v24, 1
51; CHECK-NEXT:    risblg %r0, %r0, 16, 144, 15
52; CHECK-NEXT:    rosbg %r0, %r1, 49, 49, 14
53; CHECK-NEXT:    vlgvb %r1, %v24, 2
54; CHECK-NEXT:    rosbg %r0, %r1, 50, 50, 13
55; CHECK-NEXT:    vlgvb %r1, %v24, 3
56; CHECK-NEXT:    rosbg %r0, %r1, 51, 51, 12
57; CHECK-NEXT:    vlgvb %r1, %v24, 4
58; CHECK-NEXT:    rosbg %r0, %r1, 52, 52, 11
59; CHECK-NEXT:    vlgvb %r1, %v24, 5
60; CHECK-NEXT:    rosbg %r0, %r1, 53, 53, 10
61; CHECK-NEXT:    vlgvb %r1, %v24, 6
62; CHECK-NEXT:    rosbg %r0, %r1, 54, 54, 9
63; CHECK-NEXT:    vlgvb %r1, %v24, 7
64; CHECK-NEXT:    rosbg %r0, %r1, 55, 55, 8
65; CHECK-NEXT:    vlgvb %r1, %v24, 8
66; CHECK-NEXT:    rosbg %r0, %r1, 56, 56, 7
67; CHECK-NEXT:    vlgvb %r1, %v24, 9
68; CHECK-NEXT:    rosbg %r0, %r1, 57, 57, 6
69; CHECK-NEXT:    vlgvb %r1, %v24, 10
70; CHECK-NEXT:    rosbg %r0, %r1, 58, 58, 5
71; CHECK-NEXT:    vlgvb %r1, %v24, 11
72; CHECK-NEXT:    rosbg %r0, %r1, 59, 59, 4
73; CHECK-NEXT:    vlgvb %r1, %v24, 12
74; CHECK-NEXT:    rosbg %r0, %r1, 60, 60, 3
75; CHECK-NEXT:    vlgvb %r1, %v24, 13
76; CHECK-NEXT:    rosbg %r0, %r1, 61, 61, 2
77; CHECK-NEXT:    vlgvb %r1, %v24, 14
78; CHECK-NEXT:    rosbg %r0, %r1, 62, 62, 1
79; CHECK-NEXT:    vlgvb %r1, %v24, 15
80; CHECK-NEXT:    rosbg %r0, %r1, 63, 63, 0
81; CHECK-NEXT:    llhr %r2, %r0
82; CHECK-NEXT:    aghi %r15, 168
83; CHECK-NEXT:    br %r14
84{
85  %res = bitcast <16 x i1> %src to i16
86  ret i16 %res
87}
88
89; Truncate a <8 x i32> vector to <8 x i31> and store it (test splitting).
90define void @fun2(<8 x i32> %src, ptr %p)
91; CHECK-LABEL: fun2:
92; CHECK:       # %bb.0:
93; CHECK-NEXT:    vlgvf %r0, %v26, 3
94; CHECK-NEXT:    vlvgp %v0, %r0, %r0
95; CHECK-NEXT:    srl %r0, 8
96; CHECK-NEXT:    vsteb %v0, 30(%r2), 15
97; CHECK-NEXT:    vlvgp %v1, %r0, %r0
98; CHECK-NEXT:    vsteh %v1, 28(%r2), 7
99; CHECK-NEXT:    larl %r1, .LCPI2_0
100; CHECK-NEXT:    vl %v1, 0(%r1), 3
101; CHECK-NEXT:    vlgvf %r0, %v26, 2
102; CHECK-NEXT:    larl %r1, .LCPI2_1
103; CHECK-NEXT:    vl %v2, 0(%r1), 3
104; CHECK-NEXT:    vn %v0, %v0, %v1
105; CHECK-NEXT:    vlvgp %v1, %r0, %r0
106; CHECK-NEXT:    vn %v1, %v1, %v2
107; CHECK-NEXT:    vrepib %v3, 31
108; CHECK-NEXT:    vslb %v1, %v1, %v3
109; CHECK-NEXT:    vsl %v1, %v1, %v3
110; CHECK-NEXT:    vo %v0, %v1, %v0
111; CHECK-NEXT:    vrepib %v3, 24
112; CHECK-NEXT:    vlgvf %r0, %v24, 3
113; CHECK-NEXT:    vsrlb %v0, %v0, %v3
114; CHECK-NEXT:    vstef %v0, 24(%r2), 3
115; CHECK-NEXT:    vlvgp %v0, %r0, %r0
116; CHECK-NEXT:    vrepib %v3, 124
117; CHECK-NEXT:    vlgvf %r0, %v26, 0
118; CHECK-NEXT:    vslb %v4, %v0, %v3
119; CHECK-NEXT:    vsl %v3, %v4, %v3
120; CHECK-NEXT:    vlvgp %v4, %r0, %r0
121; CHECK-NEXT:    vn %v4, %v4, %v2
122; CHECK-NEXT:    vlgvf %r0, %v26, 1
123; CHECK-NEXT:    larl %r1, .LCPI2_2
124; CHECK-NEXT:    vrepib %v5, 93
125; CHECK-NEXT:    vslb %v4, %v4, %v5
126; CHECK-NEXT:    vsl %v4, %v4, %v5
127; CHECK-NEXT:    vo %v3, %v3, %v4
128; CHECK-NEXT:    vlvgp %v4, %r0, %r0
129; CHECK-NEXT:    vlgvf %r0, %v24, 0
130; CHECK-NEXT:    vn %v4, %v4, %v2
131; CHECK-NEXT:    vrepib %v5, 62
132; CHECK-NEXT:    vslb %v4, %v4, %v5
133; CHECK-NEXT:    vsl %v4, %v4, %v5
134; CHECK-NEXT:    vo %v4, %v3, %v4
135; CHECK-NEXT:    vo %v1, %v4, %v1
136; CHECK-NEXT:    vrepib %v4, 56
137; CHECK-NEXT:    vrepib %v5, 58
138; CHECK-NEXT:    vsrlb %v1, %v1, %v4
139; CHECK-NEXT:    vsteg %v1, 16(%r2), 1
140; CHECK-NEXT:    vrepib %v1, 120
141; CHECK-NEXT:    vrepib %v4, 89
142; CHECK-NEXT:    vsrlb %v1, %v3, %v1
143; CHECK-NEXT:    vlvgp %v3, %r0, %r0
144; CHECK-NEXT:    vlgvf %r0, %v24, 1
145; CHECK-NEXT:    vslb %v3, %v3, %v4
146; CHECK-NEXT:    vsl %v3, %v3, %v4
147; CHECK-NEXT:    vlvgp %v4, %r0, %r0
148; CHECK-NEXT:    vlgvf %r0, %v24, 2
149; CHECK-NEXT:    vn %v4, %v4, %v2
150; CHECK-NEXT:    vslb %v4, %v4, %v5
151; CHECK-NEXT:    vsl %v4, %v4, %v5
152; CHECK-NEXT:    vo %v3, %v3, %v4
153; CHECK-NEXT:    vlvgp %v4, %r0, %r0
154; CHECK-NEXT:    vn %v2, %v4, %v2
155; CHECK-NEXT:    vrepib %v4, 27
156; CHECK-NEXT:    vslb %v2, %v2, %v4
157; CHECK-NEXT:    vsl %v2, %v2, %v4
158; CHECK-NEXT:    vo %v2, %v3, %v2
159; CHECK-NEXT:    vl %v3, 0(%r1), 3
160; CHECK-NEXT:    vn %v0, %v0, %v3
161; CHECK-NEXT:    vrepib %v3, 4
162; CHECK-NEXT:    vsrl %v0, %v0, %v3
163; CHECK-NEXT:    vo %v0, %v2, %v0
164; CHECK-NEXT:    vrepib %v2, 8
165; CHECK-NEXT:    vslb %v0, %v0, %v2
166; CHECK-NEXT:    vo %v0, %v0, %v1
167; CHECK-NEXT:    vst %v0, 0(%r2), 4
168; CHECK-NEXT:    br %r14
169{
170  %tmp = trunc <8 x i32> %src to <8 x i31>
171  store <8 x i31> %tmp, ptr %p
172  ret void
173}
174
175; Load and store a <3 x i31> vector (test widening).
176define void @fun3(ptr %src, ptr %p)
177; CHECK-LABEL: fun3:
178; CHECK:       # %bb.0:
179; CHECK-NEXT:    vgbm %v0, 0
180; CHECK-NEXT:    vleg %v0, 0(%r2), 1
181; CHECK-NEXT:    vgbm %v1, 0
182; CHECK-NEXT:    vlef %v1, 8(%r2), 3
183; CHECK-NEXT:    vrepib %v2, 32
184; CHECK-NEXT:    vslb %v0, %v0, %v2
185; CHECK-NEXT:    vo %v0, %v1, %v0
186; CHECK-NEXT:    vstef %v0, 8(%r3), 3
187; CHECK-NEXT:    vsrlb %v0, %v0, %v2
188; CHECK-NEXT:    vsteg %v0, 0(%r3), 1
189; CHECK-NEXT:    br %r14
190{
191  %tmp = load <3 x i31>, ptr %src
192  store <3 x i31> %tmp, ptr %p
193  ret void
194}
195