1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; Test 128-bit OR in vector registers on z13 3; 4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s 5 6; Or. 7define i128 @f1(i128 %a, i128 %b) { 8; CHECK-LABEL: f1: 9; CHECK: # %bb.0: 10; CHECK-NEXT: vl %v0, 0(%r4), 3 11; CHECK-NEXT: vl %v1, 0(%r3), 3 12; CHECK-NEXT: vo %v0, %v1, %v0 13; CHECK-NEXT: vst %v0, 0(%r2), 3 14; CHECK-NEXT: br %r14 15 %res = or i128 %a, %b 16 ret i128 %res 17} 18 19; NOR. 20define i128 @f2(i128 %a, i128 %b) { 21; CHECK-LABEL: f2: 22; CHECK: # %bb.0: 23; CHECK-NEXT: vl %v0, 0(%r4), 3 24; CHECK-NEXT: vl %v1, 0(%r3), 3 25; CHECK-NEXT: vno %v0, %v1, %v0 26; CHECK-NEXT: vst %v0, 0(%r2), 3 27; CHECK-NEXT: br %r14 28 %op = or i128 %a, %b 29 %res = xor i128 %op, -1 30 ret i128 %res 31} 32 33; Complement. 34define i128 @f3(i128 %a) { 35; CHECK-LABEL: f3: 36; CHECK: # %bb.0: 37; CHECK-NEXT: vl %v0, 0(%r3), 3 38; CHECK-NEXT: vno %v0, %v0, %v0 39; CHECK-NEXT: vst %v0, 0(%r2), 3 40; CHECK-NEXT: br %r14 41 %res = xor i128 %a, -1 42 ret i128 %res 43} 44 45; Select. 46define i128 @f4(i128 %mask, i128 %true, i128 %false) { 47; CHECK-LABEL: f4: 48; CHECK: # %bb.0: 49; CHECK-NEXT: vl %v0, 0(%r3), 3 50; CHECK-NEXT: vl %v1, 0(%r5), 3 51; CHECK-NEXT: vl %v2, 0(%r4), 3 52; CHECK-NEXT: vsel %v0, %v2, %v1, %v0 53; CHECK-NEXT: vst %v0, 0(%r2), 3 54; CHECK-NEXT: br %r14 55 %notmask = xor i128 %mask, -1 56 %res1 = and i128 %true, %mask 57 %res2 = and i128 %false, %notmask 58 %res = or i128 %res1, %res2 59 ret i128 %res 60} 61