xref: /llvm-project/llvm/test/CodeGen/SystemZ/int-uadd-07.ll (revision 872276de4b8c5f13f106b79c53a27e4a6ff8ce35)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
2; Test the three-operand form of 64-bit addition.
3;
4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
5
6declare i64 @foo(i64, i64, i64)
7
8; Check ALGRK.
9define i64 @f1(i64 %dummy, i64 %a, i64 %b, ptr %flag) {
10; CHECK-LABEL: f1:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    algrk %r2, %r3, %r4
13; CHECK-NEXT:    ipm %r0
14; CHECK-NEXT:    risbg %r0, %r0, 63, 191, 35
15; CHECK-NEXT:    stg %r0, 0(%r5)
16; CHECK-NEXT:    br %r14
17  %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
18  %val = extractvalue {i64, i1} %t, 0
19  %obit = extractvalue {i64, i1} %t, 1
20  %ext = zext i1 %obit to i64
21  store i64 %ext, ptr %flag
22  ret i64 %val
23}
24
25; Check using the overflow result for a branch.
26define i64 @f2(i64 %dummy, i64 %a, i64 %b) {
27; CHECK-LABEL: f2:
28; CHECK:       # %bb.0:
29; CHECK-NEXT:    algrk %r2, %r3, %r4
30; CHECK-NEXT:    bler %r14
31; CHECK-NEXT:  .LBB1_1: # %call
32; CHECK-NEXT:    lghi %r2, 0
33; CHECK-NEXT:    jg foo@PLT
34  %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
35  %val = extractvalue {i64, i1} %t, 0
36  %obit = extractvalue {i64, i1} %t, 1
37  br i1 %obit, label %call, label %exit
38
39call:
40  %res = tail call i64 @foo(i64 0, i64 %a, i64 %b)
41  ret i64 %res
42
43exit:
44  ret i64 %val
45}
46
47; ... and the same with the inverted direction.
48define i64 @f3(i64 %dummy, i64 %a, i64 %b) {
49; CHECK-LABEL: f3:
50; CHECK:       # %bb.0:
51; CHECK-NEXT:    algrk %r2, %r3, %r4
52; CHECK-NEXT:    bnler %r14
53; CHECK-NEXT:  .LBB2_1: # %call
54; CHECK-NEXT:    lghi %r2, 0
55; CHECK-NEXT:    jg foo@PLT
56  %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
57  %val = extractvalue {i64, i1} %t, 0
58  %obit = extractvalue {i64, i1} %t, 1
59  br i1 %obit, label %exit, label %call
60
61call:
62  %res = tail call i64 @foo(i64 0, i64 %a, i64 %b)
63  ret i64 %res
64
65exit:
66  ret i64 %val
67}
68
69; Check that we can still use ALGR in obvious cases.
70define i64 @f4(i64 %a, i64 %b, ptr %flag) {
71; CHECK-LABEL: f4:
72; CHECK:       # %bb.0:
73; CHECK-NEXT:    algr %r2, %r3
74; CHECK-NEXT:    ipm %r0
75; CHECK-NEXT:    risbg %r0, %r0, 63, 191, 35
76; CHECK-NEXT:    stg %r0, 0(%r4)
77; CHECK-NEXT:    br %r14
78  %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
79  %val = extractvalue {i64, i1} %t, 0
80  %obit = extractvalue {i64, i1} %t, 1
81  %ext = zext i1 %obit to i64
82  store i64 %ext, ptr %flag
83  ret i64 %val
84}
85
86declare {i64, i1} @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
87
88