1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; Test 128-bit division and remainder in vector registers on arch15 3; 4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s 5 6; Divide signed. 7define i128 @f1(i128 %a, i128 %b) { 8; CHECK-LABEL: f1: 9; CHECK: # %bb.0: 10; CHECK-NEXT: vl %v0, 0(%r4), 3 11; CHECK-NEXT: vl %v1, 0(%r3), 3 12; CHECK-NEXT: vdq %v0, %v1, %v0, 0 13; CHECK-NEXT: vst %v0, 0(%r2), 3 14; CHECK-NEXT: br %r14 15 %res = sdiv i128 %a, %b 16 ret i128 %res 17} 18 19; Divide unsigned. 20define i128 @f2(i128 %a, i128 %b) { 21; CHECK-LABEL: f2: 22; CHECK: # %bb.0: 23; CHECK-NEXT: vl %v0, 0(%r4), 3 24; CHECK-NEXT: vl %v1, 0(%r3), 3 25; CHECK-NEXT: vdlq %v0, %v1, %v0, 0 26; CHECK-NEXT: vst %v0, 0(%r2), 3 27; CHECK-NEXT: br %r14 28 %res = udiv i128 %a, %b 29 ret i128 %res 30} 31 32; Remainder signed. 33define i128 @f3(i128 %a, i128 %b) { 34; CHECK-LABEL: f3: 35; CHECK: # %bb.0: 36; CHECK-NEXT: vl %v0, 0(%r4), 3 37; CHECK-NEXT: vl %v1, 0(%r3), 3 38; CHECK-NEXT: vrq %v0, %v1, %v0, 0 39; CHECK-NEXT: vst %v0, 0(%r2), 3 40; CHECK-NEXT: br %r14 41 %res = srem i128 %a, %b 42 ret i128 %res 43} 44 45; Remainder unsigned. 46define i128 @f4(i128 %a, i128 %b) { 47; CHECK-LABEL: f4: 48; CHECK: # %bb.0: 49; CHECK-NEXT: vl %v0, 0(%r4), 3 50; CHECK-NEXT: vl %v1, 0(%r3), 3 51; CHECK-NEXT: vrlq %v0, %v1, %v0, 0 52; CHECK-NEXT: vst %v0, 0(%r2), 3 53; CHECK-NEXT: br %r14 54 %res = urem i128 %a, %b 55 ret i128 %res 56} 57