xref: /llvm-project/llvm/test/CodeGen/SystemZ/int-cmp-63.ll (revision a65ccc1b9fe740c9f65d9cf2b627de50278aad56) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; Test 128-bit comparisons in vector registers on z13
3;
4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -verify-machineinstrs | FileCheck %s
5
6; Equality comparison.
7define i64 @f1(i128 %value1, i128 %value2, i64 %a, i64 %b) {
8; CHECK-LABEL: f1:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vl %v0, 0(%r3), 3
11; CHECK-NEXT:    vl %v1, 0(%r2), 3
12; CHECK-NEXT:    vceqgs %v0, %v1, %v0
13; CHECK-NEXT:    locgrnhe %r4, %r5
14; CHECK-NEXT:    lgr %r2, %r4
15; CHECK-NEXT:    br %r14
16  %cond = icmp eq i128 %value1, %value2
17  %res = select i1 %cond, i64 %a, i64 %b
18  ret i64 %res
19}
20
21; Inequality comparison.
22define i64 @f2(i128 %value1, i128 %value2, i64 %a, i64 %b) {
23; CHECK-LABEL: f2:
24; CHECK:       # %bb.0:
25; CHECK-NEXT:    vl %v0, 0(%r3), 3
26; CHECK-NEXT:    vl %v1, 0(%r2), 3
27; CHECK-NEXT:    vceqgs %v0, %v1, %v0
28; CHECK-NEXT:    locgre %r4, %r5
29; CHECK-NEXT:    lgr %r2, %r4
30; CHECK-NEXT:    br %r14
31  %cond = icmp ne i128 %value1, %value2
32  %res = select i1 %cond, i64 %a, i64 %b
33  ret i64 %res
34}
35
36; Signed greater-than comparison.
37define i64 @f3(i128 %value1, i128 %value2, i64 %a, i64 %b) {
38; CHECK-LABEL: f3:
39; CHECK:       # %bb.0:
40; CHECK-NEXT:    vl %v0, 0(%r3), 3
41; CHECK-NEXT:    vl %v1, 0(%r2), 3
42; CHECK-NEXT:    vecg %v0, %v1
43; CHECK-NEXT:    jlh .LBB2_2
44; CHECK-NEXT:  # %bb.1:
45; CHECK-NEXT:    vchlgs %v0, %v1, %v0
46; CHECK-NEXT:  .LBB2_2:
47; CHECK-NEXT:    locgrl %r5, %r4
48; CHECK-NEXT:    lgr %r2, %r5
49; CHECK-NEXT:    br %r14
50  %cond = icmp sgt i128 %value1, %value2
51  %res = select i1 %cond, i64 %a, i64 %b
52  ret i64 %res
53}
54
55; Signed less-than comparison.
56define i64 @f4(i128 %value1, i128 %value2, i64 %a, i64 %b) {
57; CHECK-LABEL: f4:
58; CHECK:       # %bb.0:
59; CHECK-NEXT:    vl %v0, 0(%r2), 3
60; CHECK-NEXT:    vl %v1, 0(%r3), 3
61; CHECK-NEXT:    vecg %v0, %v1
62; CHECK-NEXT:    jlh .LBB3_2
63; CHECK-NEXT:  # %bb.1:
64; CHECK-NEXT:    vchlgs %v0, %v1, %v0
65; CHECK-NEXT:  .LBB3_2:
66; CHECK-NEXT:    locgrl %r5, %r4
67; CHECK-NEXT:    lgr %r2, %r5
68; CHECK-NEXT:    br %r14
69  %cond = icmp slt i128 %value1, %value2
70  %res = select i1 %cond, i64 %a, i64 %b
71  ret i64 %res
72}
73
74; Signed greater-or-equal comparison.
75define i64 @f5(i128 %value1, i128 %value2, i64 %a, i64 %b) {
76; CHECK-LABEL: f5:
77; CHECK:       # %bb.0:
78; CHECK-NEXT:    vl %v0, 0(%r2), 3
79; CHECK-NEXT:    vl %v1, 0(%r3), 3
80; CHECK-NEXT:    vecg %v0, %v1
81; CHECK-NEXT:    jlh .LBB4_2
82; CHECK-NEXT:  # %bb.1:
83; CHECK-NEXT:    vchlgs %v0, %v1, %v0
84; CHECK-NEXT:  .LBB4_2:
85; CHECK-NEXT:    locgrnl %r5, %r4
86; CHECK-NEXT:    lgr %r2, %r5
87; CHECK-NEXT:    br %r14
88  %cond = icmp sge i128 %value1, %value2
89  %res = select i1 %cond, i64 %a, i64 %b
90  ret i64 %res
91}
92
93; Signed less-or-equal comparison.
94define i64 @f6(i128 %value1, i128 %value2, i64 %a, i64 %b) {
95; CHECK-LABEL: f6:
96; CHECK:       # %bb.0:
97; CHECK-NEXT:    vl %v0, 0(%r3), 3
98; CHECK-NEXT:    vl %v1, 0(%r2), 3
99; CHECK-NEXT:    vecg %v0, %v1
100; CHECK-NEXT:    jlh .LBB5_2
101; CHECK-NEXT:  # %bb.1:
102; CHECK-NEXT:    vchlgs %v0, %v1, %v0
103; CHECK-NEXT:  .LBB5_2:
104; CHECK-NEXT:    locgrnl %r5, %r4
105; CHECK-NEXT:    lgr %r2, %r5
106; CHECK-NEXT:    br %r14
107  %cond = icmp sle i128 %value1, %value2
108  %res = select i1 %cond, i64 %a, i64 %b
109  ret i64 %res
110}
111
112; Unsigned greater-than comparison.
113define i64 @f7(i128 %value1, i128 %value2, i64 %a, i64 %b) {
114; CHECK-LABEL: f7:
115; CHECK:       # %bb.0:
116; CHECK-NEXT:    vl %v0, 0(%r3), 3
117; CHECK-NEXT:    vl %v1, 0(%r2), 3
118; CHECK-NEXT:    veclg %v0, %v1
119; CHECK-NEXT:    jlh .LBB6_2
120; CHECK-NEXT:  # %bb.1:
121; CHECK-NEXT:    vchlgs %v0, %v1, %v0
122; CHECK-NEXT:  .LBB6_2:
123; CHECK-NEXT:    locgrl %r5, %r4
124; CHECK-NEXT:    lgr %r2, %r5
125; CHECK-NEXT:    br %r14
126  %cond = icmp ugt i128 %value1, %value2
127  %res = select i1 %cond, i64 %a, i64 %b
128  ret i64 %res
129}
130
131; Unsigned less-than comparison.
132define i64 @f8(i128 %value1, i128 %value2, i64 %a, i64 %b) {
133; CHECK-LABEL: f8:
134; CHECK:       # %bb.0:
135; CHECK-NEXT:    vl %v0, 0(%r2), 3
136; CHECK-NEXT:    vl %v1, 0(%r3), 3
137; CHECK-NEXT:    veclg %v0, %v1
138; CHECK-NEXT:    jlh .LBB7_2
139; CHECK-NEXT:  # %bb.1:
140; CHECK-NEXT:    vchlgs %v0, %v1, %v0
141; CHECK-NEXT:  .LBB7_2:
142; CHECK-NEXT:    locgrl %r5, %r4
143; CHECK-NEXT:    lgr %r2, %r5
144; CHECK-NEXT:    br %r14
145  %cond = icmp ult i128 %value1, %value2
146  %res = select i1 %cond, i64 %a, i64 %b
147  ret i64 %res
148}
149
150; Unsigned greater-or-equal comparison.
151define i64 @f9(i128 %value1, i128 %value2, i64 %a, i64 %b) {
152; CHECK-LABEL: f9:
153; CHECK:       # %bb.0:
154; CHECK-NEXT:    vl %v0, 0(%r2), 3
155; CHECK-NEXT:    vl %v1, 0(%r3), 3
156; CHECK-NEXT:    veclg %v0, %v1
157; CHECK-NEXT:    jlh .LBB8_2
158; CHECK-NEXT:  # %bb.1:
159; CHECK-NEXT:    vchlgs %v0, %v1, %v0
160; CHECK-NEXT:  .LBB8_2:
161; CHECK-NEXT:    locgrnl %r5, %r4
162; CHECK-NEXT:    lgr %r2, %r5
163; CHECK-NEXT:    br %r14
164  %cond = icmp uge i128 %value1, %value2
165  %res = select i1 %cond, i64 %a, i64 %b
166  ret i64 %res
167}
168
169; Unsigned less-or-equal comparison.
170define i64 @f10(i128 %value1, i128 %value2, i64 %a, i64 %b) {
171; CHECK-LABEL: f10:
172; CHECK:       # %bb.0:
173; CHECK-NEXT:    vl %v0, 0(%r3), 3
174; CHECK-NEXT:    vl %v1, 0(%r2), 3
175; CHECK-NEXT:    veclg %v0, %v1
176; CHECK-NEXT:    jlh .LBB9_2
177; CHECK-NEXT:  # %bb.1:
178; CHECK-NEXT:    vchlgs %v0, %v1, %v0
179; CHECK-NEXT:  .LBB9_2:
180; CHECK-NEXT:    locgrnl %r5, %r4
181; CHECK-NEXT:    lgr %r2, %r5
182; CHECK-NEXT:    br %r14
183  %cond = icmp ule i128 %value1, %value2
184  %res = select i1 %cond, i64 %a, i64 %b
185  ret i64 %res
186}
187
188; Use VTM for "x & y == 0" comparison.
189define i64 @f11(i128 %value1, i128 %value2, i64 %a, i64 %b) {
190; CHECK-LABEL: f11:
191; CHECK:       # %bb.0:
192; CHECK-NEXT:    vl %v0, 0(%r3), 3
193; CHECK-NEXT:    vl %v1, 0(%r2), 3
194; CHECK-NEXT:    vtm %v1, %v0
195; CHECK-NEXT:    locgrnhe %r4, %r5
196; CHECK-NEXT:    lgr %r2, %r4
197; CHECK-NEXT:    br %r14
198  %and = and i128 %value1, %value2
199  %cond = icmp eq i128 %and, 0
200  %res = select i1 %cond, i64 %a, i64 %b
201  ret i64 %res
202}
203
204; Use VTM for "x & y != 0" comparison.
205define i64 @f12(i128 %value1, i128 %value2, i64 %a, i64 %b) {
206; CHECK-LABEL: f12:
207; CHECK:       # %bb.0:
208; CHECK-NEXT:    vl %v0, 0(%r3), 3
209; CHECK-NEXT:    vl %v1, 0(%r2), 3
210; CHECK-NEXT:    vtm %v1, %v0
211; CHECK-NEXT:    locgre %r4, %r5
212; CHECK-NEXT:    lgr %r2, %r4
213; CHECK-NEXT:    br %r14
214  %and = and i128 %value1, %value2
215  %cond = icmp ne i128 %and, 0
216  %res = select i1 %cond, i64 %a, i64 %b
217  ret i64 %res
218}
219
220; Select between i128 values.
221define i128 @f13(i64 %value1, i64 %value2, i128 %a, i128 %b) {
222; CHECK-LABEL: f13:
223; CHECK:       # %bb.0:
224; CHECK-NEXT:    vl %v0, 0(%r5), 3
225; CHECK-NEXT:    cgrje %r3, %r4, .LBB12_2
226; CHECK-NEXT:  # %bb.1:
227; CHECK-NEXT:    vl %v1, 0(%r6), 3
228; CHECK-NEXT:    vaq %v0, %v0, %v1
229; CHECK-NEXT:  .LBB12_2:
230; CHECK-NEXT:    vst %v0, 0(%r2), 3
231; CHECK-NEXT:    br %r14
232  %cond = icmp eq i64 %value1, %value2
233  %sum = add i128 %a, %b
234  %res = select i1 %cond, i128 %a, i128 %sum
235  ret i128 %res
236}
237
238