xref: /llvm-project/llvm/test/CodeGen/SystemZ/int-abs-03.ll (revision 8424bf207efd89eacf2fe893b67be98d535e1db6)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; Test 128-bit absolute value in vector registers on arch15
3;
4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
5
6define i128 @f1(i128 %src) {
7; CHECK-LABEL: f1:
8; CHECK:       # %bb.0:
9; CHECK-NEXT:    vl %v0, 0(%r3), 3
10; CHECK-NEXT:    vlpq %v0, %v0
11; CHECK-NEXT:    vst %v0, 0(%r2), 3
12; CHECK-NEXT:    br %r14
13  %cmp = icmp slt i128 %src, 0
14  %neg = sub i128 0, %src
15  %res = select i1 %cmp, i128 %neg, i128 %src
16  ret i128 %res
17}
18