1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=s390x-linux-gnu -no-integrated-as < %s | FileCheck %s 3; 4 5; Test i128 (tied) operands. 6 7define i32 @fun0(ptr %p1, i32 signext %l1, ptr %p2, i32 signext %l2, i8 zeroext %pad) { 8; CHECK-LABEL: fun0: 9; CHECK: # %bb.0: # %entry 10; CHECK-NEXT: lgr %r0, %r5 11; CHECK-NEXT: # kill: def $r4d killed $r4d def $r4q 12; CHECK-NEXT: lgr %r1, %r3 13; CHECK-NEXT: # kill: def $r2d killed $r2d def $r2q 14; CHECK-NEXT: sllg %r5, %r6, 24 15; CHECK-NEXT: rosbg %r5, %r0, 40, 63, 0 16; CHECK-NEXT: risbg %r3, %r1, 40, 191, 0 17; CHECK-NEXT: #APP 18; CHECK-NEXT: clcl %r2, %r4 19; CHECK-NEXT: #NO_APP 20; CHECK-NEXT: ogr %r3, %r5 21; CHECK-NEXT: risbg %r0, %r3, 40, 191, 0 22; CHECK-NEXT: ipm %r2 23; CHECK-NEXT: afi %r2, -268435456 24; CHECK-NEXT: srl %r2, 31 25; CHECK-NEXT: br %r14 26entry: 27 %0 = ptrtoint ptr %p1 to i64 28 %1 = ptrtoint ptr %p2 to i64 29 %and5 = and i32 %l2, 16777215 30 %2 = zext i32 %and5 to i64 31 %conv7 = zext i8 %pad to i64 32 %shl = shl nuw nsw i64 %conv7, 24 33 %or = or i64 %shl, %2 34 %u1.sroa.0.0.insert.ext = zext i64 %0 to i128 35 %u1.sroa.0.0.insert.shift = shl nuw i128 %u1.sroa.0.0.insert.ext, 64 36 %3 = and i32 %l1, 16777215 37 %u1.sroa.0.0.insert.mask = zext i32 %3 to i128 38 %u1.sroa.0.0.insert.insert = or i128 %u1.sroa.0.0.insert.shift, %u1.sroa.0.0.insert.mask 39 %u2.sroa.5.0.insert.ext = zext i64 %or to i128 40 %u2.sroa.0.0.insert.ext = zext i64 %1 to i128 41 %u2.sroa.0.0.insert.shift = shl nuw i128 %u2.sroa.0.0.insert.ext, 64 42 %u2.sroa.0.0.insert.insert = or i128 %u2.sroa.0.0.insert.shift, %u2.sroa.5.0.insert.ext 43 %4 = tail call { i128, i128 } asm "clcl $0, $1", "=r,=r,0,1"(i128 %u1.sroa.0.0.insert.insert, i128 %u2.sroa.0.0.insert.insert) 44 %asmresult = extractvalue { i128, i128 } %4, 0 45 %asmresult11 = extractvalue { i128, i128 } %4, 1 46 %5 = or i128 %asmresult, %asmresult11 47 %6 = and i128 %5, 16777215 48 %7 = icmp eq i128 %6, 0 49 %land.ext = zext i1 %7 to i32 50 ret i32 %land.ext 51} 52 53; Test a phys-reg def. 54define void @fun1(ptr %Src, ptr %Dst) { 55; CHECK-LABEL: fun1: 56; CHECK: # %bb.0: # %entry 57; CHECK-NEXT: #APP 58; CHECK-NEXT: BLA %r4 59; CHECK-NEXT: #NO_APP 60; CHECK-NEXT: stg %r5, 8(%r3) 61; CHECK-NEXT: stg %r4, 0(%r3) 62; CHECK-NEXT: br %r14 63entry: 64 %IAsm = call i128 asm "BLA $0", "={r4}"() 65 store volatile i128 %IAsm, ptr %Dst 66 ret void 67} 68 69; Test a phys-reg use. 70define void @fun2(ptr %Src, ptr %Dst) { 71; CHECK-LABEL: fun2: 72; CHECK: # %bb.0: # %entry 73; CHECK-NEXT: lg %r5, 8(%r2) 74; CHECK-NEXT: lg %r4, 0(%r2) 75; CHECK-NEXT: #APP 76; CHECK-NEXT: BLA %r4 77; CHECK-NEXT: #NO_APP 78; CHECK-NEXT: br %r14 79entry: 80 %L = load i128, ptr %Src 81 call void asm "BLA $0", "{r4}"(i128 %L) 82 ret void 83} 84 85; Test phys-reg use and phys-reg def. 86define void @fun3(ptr %Src, ptr %Dst) { 87; CHECK-LABEL: fun3: 88; CHECK: # %bb.0: # %entry 89; CHECK-NEXT: lg %r1, 8(%r2) 90; CHECK-NEXT: lg %r0, 0(%r2) 91; CHECK-NEXT: #APP 92; CHECK-NEXT: BLA %r4, %r0 93; CHECK-NEXT: #NO_APP 94; CHECK-NEXT: stg %r5, 8(%r3) 95; CHECK-NEXT: stg %r4, 0(%r3) 96; CHECK-NEXT: br %r14 97entry: 98 %L = load i128, ptr %Src 99 %IAsm = call i128 asm "BLA $0, $1", "={r4},{r0}"(i128 %L) 100 store volatile i128 %IAsm, ptr %Dst 101 ret void 102} 103 104; Test a tied phys-reg. 105define void @fun4(ptr %Src, ptr %Dst) { 106; CHECK-LABEL: fun4: 107; CHECK: # %bb.0: # %entry 108; CHECK-NEXT: lg %r5, 8(%r2) 109; CHECK-NEXT: lg %r4, 0(%r2) 110; CHECK-NEXT: #APP 111; CHECK-NEXT: BLA %r4, %r4 112; CHECK-NEXT: #NO_APP 113; CHECK-NEXT: stg %r5, 8(%r3) 114; CHECK-NEXT: stg %r4, 0(%r3) 115; CHECK-NEXT: br %r14 116entry: 117 %L = load i128, ptr %Src 118 %IAsm = call i128 asm "BLA $0, $1", "={r4},0"(i128 %L) 119 store volatile i128 %IAsm, ptr %Dst 120 ret void 121} 122 123; Test access of the odd register using 'N'. 124define i64 @fun5(i64 %b) { 125; CHECK-LABEL: fun5: 126; CHECK: # %bb.0: # %entry 127; CHECK-NEXT: lgr %r1, %r2 128; CHECK-NEXT: lghi %r0, 0 129; CHECK-NEXT: #APP 130; CHECK-NEXT: lgr %r2,%r1 131; CHECK-NEXT: #NO_APP 132; CHECK-NEXT: br %r14 133entry: 134 %Ins = zext i64 %b to i128 135 %Res = tail call i64 asm "\09lgr\09$0,${1:N}", "=d,d"(i128 %Ins) 136 ret i64 %Res 137} 138 139; Test 'N' with multiple accesses to the same operand and i128 result. 140@V128 = global i128 0, align 16 141define i32 @fun6() { 142; CHECK-LABEL: fun6: 143; CHECK: # %bb.0: # %entry 144; CHECK-NEXT: lgrl %r1, V128@GOT 145; CHECK-NEXT: lg %r3, 8(%r1) 146; CHECK-NEXT: lg %r2, 0(%r1) 147; CHECK-NEXT: #APP 148; CHECK-NEXT: ltgr %r3,%r3 149; CHECK-NEXT: #NO_APP 150; CHECK-NEXT: stg %r2, 0(%r1) 151; CHECK-NEXT: stg %r3, 8(%r1) 152; CHECK-NEXT: br %r14 153entry: 154 %0 = load i128, ptr @V128 155 %1 = tail call i128 asm "ltgr ${0:N},${0:N}", "=&d,0"(i128 %0) 156 store i128 %1, ptr @V128 157 ret i32 undef 158} 159