1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z15 < %s | FileCheck %s --check-prefixes=CHECK,Z15 3; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 < %s | FileCheck %s --check-prefixes=CHECK,Z13 4; 5; Test inline assembly where the operand is bitcasted. 6 7define signext i32 @int_and_f(i32 signext %cc_dep1) { 8; CHECK-LABEL: int_and_f: 9; CHECK: # %bb.0: # %entry 10; CHECK-NEXT: vlvgf %v0, %r2, 0 11; CHECK-NEXT: #APP 12; CHECK-NEXT: #NO_APP 13; CHECK-NEXT: vlgvf %r0, %v0, 0 14; CHECK-NEXT: lgfr %r2, %r0 15; CHECK-NEXT: br %r14 16entry: 17 %0 = tail call i32 asm sideeffect "", "=f,0"(i32 %cc_dep1) 18 ret i32 %0 19} 20 21define i64 @long_and_f(i64 %cc_dep1) { 22; CHECK-LABEL: long_and_f: 23; CHECK: # %bb.0: # %entry 24; CHECK-NEXT: ldgr %f0, %r2 25; CHECK-NEXT: #APP 26; CHECK-NEXT: #NO_APP 27; CHECK-NEXT: lgdr %r2, %f0 28; CHECK-NEXT: br %r14 29entry: 30 %0 = tail call i64 asm sideeffect "", "=f,0"(i64 %cc_dep1) 31 ret i64 %0 32} 33 34define void @__int128_and_f(ptr noalias nocapture writeonly sret(i128) align 8 %agg.result, ptr %0) { 35; Z15-LABEL: __int128_and_f: 36; Z15: # %bb.0: # %entry 37; Z15-NEXT: vl %v0, 0(%r3), 3 38; Z15-NEXT: vrepg %v2, %v0, 1 39; Z15-NEXT: #APP 40; Z15-NEXT: #NO_APP 41; Z15-NEXT: vmrhg %v0, %v0, %v2 42; Z15-NEXT: vst %v0, 0(%r2), 3 43; Z15-NEXT: br %r14 44; 45; Z13-LABEL: __int128_and_f: 46; Z13: # %bb.0: # %entry 47; Z13-NEXT: ld %f0, 0(%r3) 48; Z13-NEXT: ld %f2, 8(%r3) 49; Z13-NEXT: #APP 50; Z13-NEXT: #NO_APP 51; Z13-NEXT: std %f0, 0(%r2) 52; Z13-NEXT: std %f2, 8(%r2) 53; Z13-NEXT: br %r14 54entry: 55 %cc_dep1 = load i128, ptr %0, align 8 56 %1 = tail call i128 asm sideeffect "", "=f,0"(i128 %cc_dep1) 57 store i128 %1, ptr %agg.result, align 8 58 ret void 59} 60 61define signext i32 @int_and_v(i32 signext %cc_dep1) { 62; CHECK-LABEL: int_and_v: 63; CHECK: # %bb.0: # %entry 64; CHECK-NEXT: vlvgf %v0, %r2, 0 65; CHECK-NEXT: #APP 66; CHECK-NEXT: #NO_APP 67; CHECK-NEXT: vlgvf %r0, %v0, 0 68; CHECK-NEXT: lgfr %r2, %r0 69; CHECK-NEXT: br %r14 70entry: 71 %0 = tail call i32 asm sideeffect "", "=v,0"(i32 %cc_dep1) 72 ret i32 %0 73} 74 75define i64 @long_and_v(i64 %cc_dep1) { 76; CHECK-LABEL: long_and_v: 77; CHECK: # %bb.0: # %entry 78; CHECK-NEXT: ldgr %f0, %r2 79; CHECK-NEXT: #APP 80; CHECK-NEXT: #NO_APP 81; CHECK-NEXT: lgdr %r2, %f0 82; CHECK-NEXT: br %r14 83entry: 84 %0 = tail call i64 asm sideeffect "", "=v,0"(i64 %cc_dep1) 85 ret i64 %0 86} 87 88define void @__int128_and_v(ptr noalias nocapture writeonly sret(i128) align 8 %agg.result, ptr %0) { 89; CHECK-LABEL: __int128_and_v: 90; CHECK: # %bb.0: # %entry 91; CHECK-NEXT: vl %v0, 0(%r3), 3 92; CHECK-NEXT: #APP 93; CHECK-NEXT: #NO_APP 94; CHECK-NEXT: vst %v0, 0(%r2), 3 95; CHECK-NEXT: br %r14 96entry: 97 %cc_dep1 = load i128, ptr %0, align 8 98 %1 = tail call i128 asm sideeffect "", "=v,0"(i128 %cc_dep1) 99 store i128 %1, ptr %agg.result, align 8 100 ret void 101} 102 103define float @float_and_r(float %cc_dep1) { 104; CHECK-LABEL: float_and_r: 105; CHECK: # %bb.0: # %entry 106; CHECK-NEXT: vlgvf %r0, %v0, 0 107; CHECK-NEXT: #APP 108; CHECK-NEXT: #NO_APP 109; CHECK-NEXT: vlvgf %v0, %r0, 0 110; CHECK-NEXT: br %r14 111entry: 112 %0 = tail call float asm sideeffect "", "=r,0"(float %cc_dep1) 113 ret float %0 114} 115 116define double @double_and_r(double %cc_dep1) { 117; CHECK-LABEL: double_and_r: 118; CHECK: # %bb.0: # %entry 119; CHECK-NEXT: lgdr %r0, %f0 120; CHECK-NEXT: #APP 121; CHECK-NEXT: #NO_APP 122; CHECK-NEXT: ldgr %f0, %r0 123; CHECK-NEXT: br %r14 124entry: 125 %0 = tail call double asm sideeffect "", "=r,0"(double %cc_dep1) 126 ret double %0 127} 128 129define void @longdouble_and_r(ptr noalias nocapture writeonly sret(fp128) align 8 %agg.result, ptr %0) { 130; CHECK-LABEL: longdouble_and_r: 131; CHECK: # %bb.0: # %entry 132; CHECK-NEXT: lg %r1, 8(%r3) 133; CHECK-NEXT: lg %r0, 0(%r3) 134; CHECK-NEXT: #APP 135; CHECK-NEXT: #NO_APP 136; CHECK-NEXT: stg %r1, 8(%r2) 137; CHECK-NEXT: stg %r0, 0(%r2) 138; CHECK-NEXT: br %r14 139entry: 140 %cc_dep1 = load fp128, ptr %0, align 8 141 %1 = tail call fp128 asm sideeffect "", "=r,0"(fp128 %cc_dep1) 142 store fp128 %1, ptr %agg.result, align 8 143 ret void 144} 145 146define float @float_and_v(float %cc_dep1) { 147; CHECK-LABEL: float_and_v: 148; CHECK: # %bb.0: # %entry 149; CHECK-NEXT: #APP 150; CHECK-NEXT: #NO_APP 151; CHECK-NEXT: br %r14 152entry: 153 %0 = tail call float asm sideeffect "", "=v,0"(float %cc_dep1) 154 ret float %0 155} 156 157define double @double_and_v(double %cc_dep1) { 158; CHECK-LABEL: double_and_v: 159; CHECK: # %bb.0: # %entry 160; CHECK-NEXT: #APP 161; CHECK-NEXT: #NO_APP 162; CHECK-NEXT: br %r14 163entry: 164 %0 = tail call double asm sideeffect "", "=v,0"(double %cc_dep1) 165 ret double %0 166} 167 168define void @longdouble_and_v(ptr noalias nocapture writeonly sret(fp128) align 8 %agg.result, ptr %0) { 169; CHECK-LABEL: longdouble_and_v: 170; CHECK: # %bb.0: # %entry 171; CHECK-NEXT: vl %v0, 0(%r3), 3 172; CHECK-NEXT: #APP 173; CHECK-NEXT: #NO_APP 174; CHECK-NEXT: vst %v0, 0(%r2), 3 175; CHECK-NEXT: br %r14 176entry: 177 %cc_dep1 = load fp128, ptr %0, align 8 178 %1 = tail call fp128 asm sideeffect "", "=v,0"(fp128 %cc_dep1) 179 store fp128 %1, ptr %agg.result, align 8 180 ret void 181} 182 183define <2 x i16> @vec32_and_r(<2 x i16> %cc_dep1) { 184; CHECK-LABEL: vec32_and_r: 185; CHECK: # %bb.0: # %entry 186; CHECK-NEXT: vlgvf %r0, %v24, 0 187; CHECK-NEXT: #APP 188; CHECK-NEXT: #NO_APP 189; CHECK-NEXT: vlvgf %v24, %r0, 0 190; CHECK-NEXT: br %r14 191entry: 192 %0 = tail call <2 x i16> asm sideeffect "", "=r,0"(<2 x i16> %cc_dep1) 193 ret <2 x i16> %0 194} 195 196define <2 x i32> @vec64_and_r(<2 x i32> %cc_dep1) { 197; CHECK-LABEL: vec64_and_r: 198; CHECK: # %bb.0: # %entry 199; CHECK-NEXT: vlgvg %r0, %v24, 0 200; CHECK-NEXT: #APP 201; CHECK-NEXT: #NO_APP 202; CHECK-NEXT: vlvgg %v24, %r0, 0 203; CHECK-NEXT: br %r14 204entry: 205 %0 = tail call <2 x i32> asm sideeffect "", "=r,0"(<2 x i32> %cc_dep1) 206 ret <2 x i32> %0 207} 208 209define <4 x i32> @vec128_and_r(<4 x i32> %cc_dep1) { 210; CHECK-LABEL: vec128_and_r: 211; CHECK: # %bb.0: # %entry 212; CHECK-NEXT: vlgvg %r1, %v24, 1 213; CHECK-NEXT: vlgvg %r0, %v24, 0 214; CHECK-NEXT: #APP 215; CHECK-NEXT: #NO_APP 216; CHECK-NEXT: vlvgp %v24, %r0, %r1 217; CHECK-NEXT: br %r14 218entry: 219 %0 = tail call <4 x i32> asm sideeffect "", "=r,0"(<4 x i32> %cc_dep1) 220 ret <4 x i32> %0 221} 222 223define <2 x i16> @vec32_and_f(<2 x i16> %cc_dep1) { 224; CHECK-LABEL: vec32_and_f: 225; CHECK: # %bb.0: # %entry 226; CHECK-NEXT: vlr %v0, %v24 227; CHECK-NEXT: #APP 228; CHECK-NEXT: #NO_APP 229; CHECK-NEXT: vlr %v24, %v0 230; CHECK-NEXT: br %r14 231entry: 232 %0 = tail call <2 x i16> asm sideeffect "", "=f,0"(<2 x i16> %cc_dep1) 233 ret <2 x i16> %0 234} 235 236define <2 x i32> @vec64_and_f(<2 x i32> %cc_dep1) { 237; CHECK-LABEL: vec64_and_f: 238; CHECK: # %bb.0: # %entry 239; CHECK-NEXT: vlr %v0, %v24 240; CHECK-NEXT: #APP 241; CHECK-NEXT: #NO_APP 242; CHECK-NEXT: vlr %v24, %v0 243; CHECK-NEXT: br %r14 244entry: 245 %0 = tail call <2 x i32> asm sideeffect "", "=f,0"(<2 x i32> %cc_dep1) 246 ret <2 x i32> %0 247} 248 249define <4 x i32> @vec128_and_f(<4 x i32> %cc_dep1) { 250; CHECK-LABEL: vec128_and_f: 251; CHECK: # %bb.0: # %entry 252; CHECK-NEXT: vlr %v0, %v24 253; CHECK-NEXT: vrepg %v2, %v24, 1 254; CHECK-NEXT: #APP 255; CHECK-NEXT: #NO_APP 256; CHECK-NEXT: vmrhg %v24, %v0, %v2 257; CHECK-NEXT: br %r14 258entry: 259 %0 = tail call <4 x i32> asm sideeffect "", "=f,0"(<4 x i32> %cc_dep1) 260 ret <4 x i32> %0 261} 262 263