1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; RUN: llc -mtriple=s390x-linux-gnu -mcpu=zEC12 < %s | FileCheck %s 3; 4; Test inline assembly where the operand is bitcasted. 5 6define signext i32 @int_and_f(i32 signext %cc_dep1) { 7; CHECK-LABEL: int_and_f: 8; CHECK: # %bb.0: # %entry 9; CHECK-NEXT: risbhg %r0, %r2, 0, 159, 32 10; CHECK-NEXT: ldgr %f0, %r0 11; CHECK-NEXT: #APP 12; CHECK-NEXT: #NO_APP 13; CHECK-NEXT: lgdr %r0, %f0 14; CHECK-NEXT: risblg %r0, %r0, 0, 159, 32 15; CHECK-NEXT: lgfr %r2, %r0 16; CHECK-NEXT: br %r14 17entry: 18 %0 = tail call i32 asm sideeffect "", "=f,0"(i32 %cc_dep1) 19 ret i32 %0 20} 21 22define i64 @long_and_f(i64 %cc_dep1) { 23; CHECK-LABEL: long_and_f: 24; CHECK: # %bb.0: # %entry 25; CHECK-NEXT: ldgr %f0, %r2 26; CHECK-NEXT: #APP 27; CHECK-NEXT: #NO_APP 28; CHECK-NEXT: lgdr %r2, %f0 29; CHECK-NEXT: br %r14 30entry: 31 %0 = tail call i64 asm sideeffect "", "=f,0"(i64 %cc_dep1) 32 ret i64 %0 33} 34 35define void @__int128_and_f(ptr noalias nocapture writeonly sret(i128) align 8 %agg.result, ptr %0) { 36; CHECK-LABEL: __int128_and_f: 37; CHECK: # %bb.0: # %entry 38; CHECK-NEXT: ld %f0, 0(%r3) 39; CHECK-NEXT: ld %f2, 8(%r3) 40; CHECK-NEXT: #APP 41; CHECK-NEXT: #NO_APP 42; CHECK-NEXT: std %f0, 0(%r2) 43; CHECK-NEXT: std %f2, 8(%r2) 44; CHECK-NEXT: br %r14 45entry: 46 %cc_dep1 = load i128, ptr %0, align 8 47 %1 = tail call i128 asm sideeffect "", "=f,0"(i128 %cc_dep1) 48 store i128 %1, ptr %agg.result, align 8 49 ret void 50} 51 52define float @float_and_r(float %cc_dep1) { 53; CHECK-LABEL: float_and_r: 54; CHECK: # %bb.0: # %entry 55; CHECK-NEXT: # kill: def $f0s killed $f0s def $f0d 56; CHECK-NEXT: lgdr %r0, %f0 57; CHECK-NEXT: risblg %r0, %r0, 0, 159, 32 58; CHECK-NEXT: #APP 59; CHECK-NEXT: #NO_APP 60; CHECK-NEXT: risbhg %r0, %r0, 0, 159, 32 61; CHECK-NEXT: ldgr %f0, %r0 62; CHECK-NEXT: # kill: def $f0s killed $f0s killed $f0d 63; CHECK-NEXT: br %r14 64entry: 65 %0 = tail call float asm sideeffect "", "=r,0"(float %cc_dep1) 66 ret float %0 67} 68 69define double @double_and_r(double %cc_dep1) { 70; CHECK-LABEL: double_and_r: 71; CHECK: # %bb.0: # %entry 72; CHECK-NEXT: lgdr %r0, %f0 73; CHECK-NEXT: #APP 74; CHECK-NEXT: #NO_APP 75; CHECK-NEXT: ldgr %f0, %r0 76; CHECK-NEXT: br %r14 77entry: 78 %0 = tail call double asm sideeffect "", "=r,0"(double %cc_dep1) 79 ret double %0 80} 81 82define void @longdouble_and_r(ptr noalias nocapture writeonly sret(fp128) align 8 %agg.result, ptr %0) { 83; CHECK-LABEL: longdouble_and_r: 84; CHECK: # %bb.0: # %entry 85; CHECK-NEXT: lg %r1, 8(%r3) 86; CHECK-NEXT: lg %r0, 0(%r3) 87; CHECK-NEXT: #APP 88; CHECK-NEXT: #NO_APP 89; CHECK-NEXT: stg %r1, 8(%r2) 90; CHECK-NEXT: stg %r0, 0(%r2) 91; CHECK-NEXT: br %r14 92entry: 93 %cc_dep1 = load fp128, ptr %0, align 8 94 %1 = tail call fp128 asm sideeffect "", "=r,0"(fp128 %cc_dep1) 95 store fp128 %1, ptr %agg.result, align 8 96 ret void 97} 98 99define <2 x i16> @vec32_and_r(<2 x i16> %cc_dep1) { 100; CHECK-LABEL: vec32_and_r: 101; CHECK: # %bb.0: # %entry 102; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d 103; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 104; CHECK-NEXT: risbgn %r3, %r2, 32, 47, 16 105; CHECK-NEXT: #APP 106; CHECK-NEXT: #NO_APP 107; CHECK-NEXT: srlk %r2, %r3, 16 108; CHECK-NEXT: # kill: def $r3l killed $r3l killed $r3d 109; CHECK-NEXT: br %r14 110entry: 111 %0 = tail call <2 x i16> asm sideeffect "", "=r,0"(<2 x i16> %cc_dep1) 112 ret <2 x i16> %0 113} 114 115define <2 x i32> @vec64_and_r(<2 x i32> %cc_dep1) { 116; CHECK-LABEL: vec64_and_r: 117; CHECK: # %bb.0: # %entry 118; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 119; CHECK-NEXT: sllg %r0, %r2, 32 120; CHECK-NEXT: lr %r0, %r3 121; CHECK-NEXT: #APP 122; CHECK-NEXT: #NO_APP 123; CHECK-NEXT: lr %r3, %r0 124; CHECK-NEXT: srlg %r2, %r0, 32 125; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d 126; CHECK-NEXT: br %r14 127entry: 128 %0 = tail call <2 x i32> asm sideeffect "", "=r,0"(<2 x i32> %cc_dep1) 129 ret <2 x i32> %0 130} 131 132define <2 x i16> @vec32_and_f(<2 x i16> %cc_dep1) { 133; CHECK-LABEL: vec32_and_f: 134; CHECK: # %bb.0: # %entry 135; CHECK-NEXT: # kill: def $r3l killed $r3l def $r3d 136; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 137; CHECK-NEXT: risbgn %r3, %r2, 32, 47, 16 138; CHECK-NEXT: risbhg %r0, %r3, 0, 159, 32 139; CHECK-NEXT: ldgr %f0, %r0 140; CHECK-NEXT: #APP 141; CHECK-NEXT: #NO_APP 142; CHECK-NEXT: lgdr %r0, %f0 143; CHECK-NEXT: risblg %r3, %r0, 0, 159, 32 144; CHECK-NEXT: srlk %r2, %r3, 16 145; CHECK-NEXT: br %r14 146entry: 147 %0 = tail call <2 x i16> asm sideeffect "", "=f,0"(<2 x i16> %cc_dep1) 148 ret <2 x i16> %0 149} 150 151define <2 x i32> @vec64_and_f(<2 x i32> %cc_dep1) { 152; CHECK-LABEL: vec64_and_f: 153; CHECK: # %bb.0: # %entry 154; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 155; CHECK-NEXT: sllg %r0, %r2, 32 156; CHECK-NEXT: lr %r0, %r3 157; CHECK-NEXT: ldgr %f0, %r0 158; CHECK-NEXT: #APP 159; CHECK-NEXT: #NO_APP 160; CHECK-NEXT: lgdr %r3, %f0 161; CHECK-NEXT: srlg %r2, %r3, 32 162; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d 163; CHECK-NEXT: # kill: def $r3l killed $r3l killed $r3d 164; CHECK-NEXT: br %r14 165entry: 166 %0 = tail call <2 x i32> asm sideeffect "", "=f,0"(<2 x i32> %cc_dep1) 167 ret <2 x i32> %0 168} 169 170define <4 x i32> @vec128_and_f(<4 x i32> %cc_dep1) { 171; CHECK-LABEL: vec128_and_f: 172; CHECK: # %bb.0: # %entry 173; CHECK-NEXT: aghi %r15, -176 174; CHECK-NEXT: .cfi_def_cfa_offset 336 175; CHECK-NEXT: # kill: def $r4l killed $r4l def $r4d 176; CHECK-NEXT: sllg %r0, %r4, 32 177; CHECK-NEXT: lr %r0, %r5 178; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 179; CHECK-NEXT: stg %r0, 168(%r15) 180; CHECK-NEXT: sllg %r0, %r2, 32 181; CHECK-NEXT: lr %r0, %r3 182; CHECK-NEXT: stg %r0, 160(%r15) 183; CHECK-NEXT: ld %f0, 160(%r15) 184; CHECK-NEXT: ld %f2, 168(%r15) 185; CHECK-NEXT: #APP 186; CHECK-NEXT: #NO_APP 187; CHECK-NEXT: lgdr %r3, %f0 188; CHECK-NEXT: lgdr %r5, %f2 189; CHECK-NEXT: srlg %r2, %r3, 32 190; CHECK-NEXT: srlg %r4, %r5, 32 191; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d 192; CHECK-NEXT: # kill: def $r3l killed $r3l killed $r3d 193; CHECK-NEXT: # kill: def $r4l killed $r4l killed $r4d 194; CHECK-NEXT: # kill: def $r5l killed $r5l killed $r5d 195; CHECK-NEXT: aghi %r15, 176 196; CHECK-NEXT: br %r14 197entry: 198 %0 = tail call <4 x i32> asm sideeffect "", "=f,0"(<4 x i32> %cc_dep1) 199 ret <4 x i32> %0 200} 201 202