1; Test 32-bit floating-point addition. 2; 3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \ 4; RUN: | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s 5; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s 6 7declare float @foo() 8 9; Check register addition. 10define float @f1(float %f1, float %f2) { 11; CHECK-LABEL: f1: 12; CHECK: aebr %f0, %f2 13; CHECK: br %r14 14 %res = fadd float %f1, %f2 15 ret float %res 16} 17 18; Check the low end of the AEB range. 19define float @f2(float %f1, ptr %ptr) { 20; CHECK-LABEL: f2: 21; CHECK: aeb %f0, 0(%r2) 22; CHECK: br %r14 23 %f2 = load float, ptr %ptr 24 %res = fadd float %f1, %f2 25 ret float %res 26} 27 28; Check the high end of the aligned AEB range. 29define float @f3(float %f1, ptr %base) { 30; CHECK-LABEL: f3: 31; CHECK: aeb %f0, 4092(%r2) 32; CHECK: br %r14 33 %ptr = getelementptr float, ptr %base, i64 1023 34 %f2 = load float, ptr %ptr 35 %res = fadd float %f1, %f2 36 ret float %res 37} 38 39; Check the next word up, which needs separate address logic. 40; Other sequences besides this one would be OK. 41define float @f4(float %f1, ptr %base) { 42; CHECK-LABEL: f4: 43; CHECK: aghi %r2, 4096 44; CHECK: aeb %f0, 0(%r2) 45; CHECK: br %r14 46 %ptr = getelementptr float, ptr %base, i64 1024 47 %f2 = load float, ptr %ptr 48 %res = fadd float %f1, %f2 49 ret float %res 50} 51 52; Check negative displacements, which also need separate address logic. 53define float @f5(float %f1, ptr %base) { 54; CHECK-LABEL: f5: 55; CHECK: aghi %r2, -4 56; CHECK: aeb %f0, 0(%r2) 57; CHECK: br %r14 58 %ptr = getelementptr float, ptr %base, i64 -1 59 %f2 = load float, ptr %ptr 60 %res = fadd float %f1, %f2 61 ret float %res 62} 63 64; Check that AEB allows indices. 65define float @f6(float %f1, ptr %base, i64 %index) { 66; CHECK-LABEL: f6: 67; CHECK: sllg %r1, %r3, 2 68; CHECK: aeb %f0, 400(%r1,%r2) 69; CHECK: br %r14 70 %ptr1 = getelementptr float, ptr %base, i64 %index 71 %ptr2 = getelementptr float, ptr %ptr1, i64 100 72 %f2 = load float, ptr %ptr2 73 %res = fadd float %f1, %f2 74 ret float %res 75} 76 77; Check that additions of spilled values can use AEB rather than AEBR. 78define float @f7(ptr %ptr0) { 79; CHECK-LABEL: f7: 80; CHECK: brasl %r14, foo@PLT 81; CHECK-SCALAR: aeb %f0, 16{{[04]}}(%r15) 82; CHECK: br %r14 83 %ptr1 = getelementptr float, ptr %ptr0, i64 2 84 %ptr2 = getelementptr float, ptr %ptr0, i64 4 85 %ptr3 = getelementptr float, ptr %ptr0, i64 6 86 %ptr4 = getelementptr float, ptr %ptr0, i64 8 87 %ptr5 = getelementptr float, ptr %ptr0, i64 10 88 %ptr6 = getelementptr float, ptr %ptr0, i64 12 89 %ptr7 = getelementptr float, ptr %ptr0, i64 14 90 %ptr8 = getelementptr float, ptr %ptr0, i64 16 91 %ptr9 = getelementptr float, ptr %ptr0, i64 18 92 %ptr10 = getelementptr float, ptr %ptr0, i64 20 93 94 %val0 = load float, ptr %ptr0 95 %val1 = load float, ptr %ptr1 96 %val2 = load float, ptr %ptr2 97 %val3 = load float, ptr %ptr3 98 %val4 = load float, ptr %ptr4 99 %val5 = load float, ptr %ptr5 100 %val6 = load float, ptr %ptr6 101 %val7 = load float, ptr %ptr7 102 %val8 = load float, ptr %ptr8 103 %val9 = load float, ptr %ptr9 104 %val10 = load float, ptr %ptr10 105 106 %ret = call float @foo() 107 108 %add0 = fadd float %ret, %val0 109 %add1 = fadd float %add0, %val1 110 %add2 = fadd float %add1, %val2 111 %add3 = fadd float %add2, %val3 112 %add4 = fadd float %add3, %val4 113 %add5 = fadd float %add4, %val5 114 %add6 = fadd float %add5, %val6 115 %add7 = fadd float %add6, %val7 116 %add8 = fadd float %add7, %val8 117 %add9 = fadd float %add8, %val9 118 %add10 = fadd float %add9, %val10 119 120 ret float %add10 121} 122 123; Check that reassociation flags do not get in the way of AEB. 124define float @f8(ptr %x) { 125; CHECK-LABEL: f8: 126; CHECK: aeb %f0 127entry: 128 %0 = load float, ptr %x, align 8 129 %arrayidx1 = getelementptr inbounds float, ptr %x, i64 1 130 %1 = load float, ptr %arrayidx1, align 8 131 %add = fadd reassoc nsz arcp contract afn float %1, %0 132 ret float %add 133} 134