xref: /llvm-project/llvm/test/CodeGen/SystemZ/and-11.ll (revision a65ccc1b9fe740c9f65d9cf2b627de50278aad56)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; Test 128-bit NAND in vector registers on z14
3;
4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
5
6define i128 @f1(i128 %a, i128 %b) {
7; CHECK-LABEL: f1:
8; CHECK:       # %bb.0:
9; CHECK-NEXT:    vl %v0, 0(%r4), 3
10; CHECK-NEXT:    vl %v1, 0(%r3), 3
11; CHECK-NEXT:    vnn %v0, %v1, %v0
12; CHECK-NEXT:    vst %v0, 0(%r2), 3
13; CHECK-NEXT:    br %r14
14  %op = and i128 %a, %b
15  %res = xor i128 %op, -1
16  ret i128 %res
17}
18