1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 2; Test complex addresses with base or index truncated from 128 bit. 3; 4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s 5 6; Shift amount with base truncated from 128 bit to 32 bit. 7define void @f1(i128 %x, i32 %y, ptr %px, ptr %py) { 8; CHECK-LABEL: f1: 9; CHECK: # %bb.0: 10; CHECK-NEXT: larl %r1, .LCPI0_0 11; CHECK-NEXT: vl %v0, 0(%r2), 3 12; CHECK-NEXT: vl %v1, 0(%r1), 3 13; CHECK-NEXT: vaq %v0, %v0, %v1 14; CHECK-NEXT: vlgvf %r1, %v0, 3 15; CHECK-NEXT: srl %r3, 0(%r1) 16; CHECK-NEXT: vst %v0, 0(%r4), 3 17; CHECK-NEXT: st %r3, 0(%r5) 18; CHECK-NEXT: br %r14 19 %x1 = add i128 %x, 1 20 store i128 %x1, ptr %px, align 8 21 %amt = trunc i128 %x1 to i32 22 %y1 = lshr i32 %y, %amt 23 store i32 %y1, ptr %py, align 4 24 ret void 25} 26 27; Memory address with index truncated from 128 bit to 64 bit. 28define i8 @f2(ptr %base, ptr %p) { 29; CHECK-LABEL: f2: 30; CHECK: # %bb.0: 31; CHECK-NEXT: larl %r1, .LCPI1_0 32; CHECK-NEXT: vl %v0, 0(%r3), 3 33; CHECK-NEXT: vl %v1, 0(%r1), 3 34; CHECK-NEXT: vaq %v0, %v0, %v1 35; CHECK-NEXT: vlgvg %r1, %v0, 1 36; CHECK-NEXT: vst %v0, 0(%r3), 3 37; CHECK-NEXT: lb %r2, 0(%r1,%r2) 38; CHECK-NEXT: br %r14 39 %idx = load i128, ptr %p, align 8 40 %inc = add nsw i128 %idx, 1 41 store i128 %inc, ptr %p, align 8 42 %idxprom = trunc i128 %inc to i64 43 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %idxprom 44 %res = load i8, ptr %arrayidx, align 1 45 ret i8 %res 46} 47