xref: /llvm-project/llvm/test/CodeGen/SPIRV/structurizer/HLSLControlFlowHint-pass-check.ll (revision 380bb51b70b6d9f3da07a87f56fc3fe44bc78691) 
1; RUN: opt -passes='spirv-structurizer' -S -mtriple=spirv-unknown-unknown %s | FileCheck %s
2
3; CHECK-LABEL: define spir_func noundef i32 @test_branch
4; CHECK: call void @llvm.spv.selection.merge.p0(ptr blockaddress(@test_branch, %if.end), i32 1)
5; CHECK-NEXT: br i1 %cmp, label %if.then, label %if.else, !hlsl.controlflow.hint !{{[0-9]+}}
6define spir_func noundef i32 @test_branch(i32 noundef %X) {
7entry:
8  %X.addr = alloca i32, align 4
9  %resp = alloca i32, align 4
10  store i32 %X, ptr %X.addr, align 4
11  %0 = load i32, ptr %X.addr, align 4
12  %cmp = icmp sgt i32 %0, 0
13  br i1 %cmp, label %if.then, label %if.else, !hlsl.controlflow.hint !0
14
15if.then:                                          ; preds = %entry
16  %1 = load i32, ptr %X.addr, align 4
17  %sub = sub nsw i32 0, %1
18  store i32 %sub, ptr %resp, align 4
19  br label %if.end
20
21if.else:                                          ; preds = %entry
22  %2 = load i32, ptr %X.addr, align 4
23  %mul = mul nsw i32 %2, 2
24  store i32 %mul, ptr %resp, align 4
25  br label %if.end
26
27if.end:                                           ; preds = %if.else, %if.then
28  %3 = load i32, ptr %resp, align 4
29  ret i32 %3
30}
31
32; CHECK-LABEL: define spir_func noundef i32 @test_flatten
33; CHECK: call void @llvm.spv.selection.merge.p0(ptr blockaddress(@test_flatten, %if.end), i32 2)
34; CHECK-NEXT: br i1 %cmp, label %if.then, label %if.else, !hlsl.controlflow.hint !{{[0-9]+}}
35define spir_func noundef i32 @test_flatten(i32 noundef %X) {
36entry:
37  %X.addr = alloca i32, align 4
38  %resp = alloca i32, align 4
39  store i32 %X, ptr %X.addr, align 4
40  %0 = load i32, ptr %X.addr, align 4
41  %cmp = icmp sgt i32 %0, 0
42  br i1 %cmp, label %if.then, label %if.else, !hlsl.controlflow.hint !1
43
44if.then:                                          ; preds = %entry
45  %1 = load i32, ptr %X.addr, align 4
46  %sub = sub nsw i32 0, %1
47  store i32 %sub, ptr %resp, align 4
48  br label %if.end
49
50if.else:                                          ; preds = %entry
51  %2 = load i32, ptr %X.addr, align 4
52  %mul = mul nsw i32 %2, 2
53  store i32 %mul, ptr %resp, align 4
54  br label %if.end
55
56if.end:                                           ; preds = %if.else, %if.then
57  %3 = load i32, ptr %resp, align 4
58  ret i32 %3
59}
60; CHECK-LABEL: define spir_func noundef i32 @test_no_attr
61; CHECK: call void @llvm.spv.selection.merge.p0(ptr blockaddress(@test_no_attr, %if.end), i32 0)
62; CHECK-NEXT: br i1 %cmp, label %if.then, label %if.else
63define spir_func noundef i32 @test_no_attr(i32 noundef %X) {
64entry:
65  %X.addr = alloca i32, align 4
66  %resp = alloca i32, align 4
67  store i32 %X, ptr %X.addr, align 4
68  %0 = load i32, ptr %X.addr, align 4
69  %cmp = icmp sgt i32 %0, 0
70  br i1 %cmp, label %if.then, label %if.else
71
72if.then:                                          ; preds = %entry
73  %1 = load i32, ptr %X.addr, align 4
74  %sub = sub nsw i32 0, %1
75  store i32 %sub, ptr %resp, align 4
76  br label %if.end
77
78if.else:                                          ; preds = %entry
79  %2 = load i32, ptr %X.addr, align 4
80  %mul = mul nsw i32 %2, 2
81  store i32 %mul, ptr %resp, align 4
82  br label %if.end
83
84if.end:                                           ; preds = %if.else, %if.then
85  %3 = load i32, ptr %resp, align 4
86  ret i32 %3
87}
88
89!0 = !{!"hlsl.controlflow.hint", i32 1}
90!1 = !{!"hlsl.controlflow.hint", i32 2}
91