1; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV 2; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} 3 4declare dso_local spir_func <4 x i8> @_Z13__spirv_IsNanIDv4_aDv4_fET_T0_(<4 x float>) 5declare dso_local spir_func <4 x i8> @_Z13__spirv_IsInfIDv4_aDv4_fET_T0_(<4 x float>) 6declare dso_local spir_func <4 x i8> @_Z16__spirv_IsFiniteIDv4_aDv4_fET_T0_(<4 x float>) 7declare dso_local spir_func <4 x i8> @_Z16__spirv_IsNormalIDv4_aDv4_fET_T0_(<4 x float>) 8declare dso_local spir_func <4 x i8> @_Z18__spirv_SignBitSetIDv4_aDv4_fET_T0_(<4 x float>) 9 10; CHECK-SPIRV: %[[#TBool:]] = OpTypeBool 11; CHECK-SPIRV: %[[#TBoolVec:]] = OpTypeVector %[[#TBool]] 12 13define spir_kernel void @k() { 14entry: 15 %arg1 = alloca <4 x float>, align 16 16 %ret = alloca <4 x i8>, align 4 17 %0 = load <4 x float>, <4 x float>* %arg1, align 16 18 %call1 = call spir_func <4 x i8> @_Z13__spirv_IsNanIDv4_aDv4_fET_T0_(<4 x float> %0) 19; CHECK-SPIRV: %[[#IsNanRes:]] = OpIsNan %[[#TBoolVec]] 20; CHECK-SPIRV: %[[#SelectRes:]] = OpSelect %[[#]] %[[#IsNanRes]] 21; CHECK-SPIRV: OpStore %[[#]] %[[#SelectRes]] 22 store <4 x i8> %call1, <4 x i8>* %ret, align 4 23 %call2 = call spir_func <4 x i8> @_Z13__spirv_IsInfIDv4_aDv4_fET_T0_(<4 x float> %0) 24; CHECK-SPIRV: %[[#IsInfRes:]] = OpIsInf %[[#TBoolVec]] 25; CHECK-SPIRV: %[[#Select1Res:]] = OpSelect %[[#]] %[[#IsInfRes]] 26; CHECK-SPIRV: OpStore %[[#]] %[[#Select1Res]] 27 store <4 x i8> %call2, <4 x i8>* %ret, align 4 28 %call3 = call spir_func <4 x i8> @_Z16__spirv_IsFiniteIDv4_aDv4_fET_T0_(<4 x float> %0) 29; CHECK-SPIRV: %[[#IsFiniteRes:]] = OpIsFinite %[[#TBoolVec]] 30; CHECK-SPIRV: %[[#Select2Res:]] = OpSelect %[[#]] %[[#IsFiniteRes]] 31; CHECK-SPIRV: OpStore %[[#]] %[[#Select2Res]] 32 store <4 x i8> %call3, <4 x i8>* %ret, align 4 33 %call4 = call spir_func <4 x i8> @_Z16__spirv_IsNormalIDv4_aDv4_fET_T0_(<4 x float> %0) 34; CHECK-SPIRV: %[[#IsNormalRes:]] = OpIsNormal %[[#TBoolVec]] 35; CHECK-SPIRV: %[[#Select3Res:]] = OpSelect %[[#]] %[[#IsNormalRes]] 36; CHECK-SPIRV: OpStore %[[#]] %[[#Select3Res]] 37 store <4 x i8> %call4, <4 x i8>* %ret, align 4 38 %call5 = call spir_func <4 x i8> @_Z18__spirv_SignBitSetIDv4_aDv4_fET_T0_(<4 x float> %0) 39; CHECK-SPIRV: %[[#SignBitSetRes:]] = OpSignBitSet %[[#TBoolVec]] 40; CHECK-SPIRV: %[[#Select4Res:]] = OpSelect %[[#]] %[[#SignBitSetRes]] 41; CHECK-SPIRV: OpStore %[[#]] %[[#Select4Res]] 42 store <4 x i8> %call5, <4 x i8>* %ret, align 4 43 ret void 44} 45