xref: /llvm-project/llvm/test/CodeGen/SPIRV/branching/OpSwitchChar.ll (revision 8bfb2b6d771ce1aa817b621bc922c1ab92eda034) 
1;; __kernel void test_switch(__global int* res, uchar val)
2;; {
3;;   switch(val)
4;;   {
5;;   case 0:
6;;     *res = 1;
7;;     break;
8;;   case 1:
9;;     *res = 2;
10;;     break;
11;;   case 2:
12;;     *res = 3;
13;;     break;
14;;   }
15;; }
16
17; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
18
19; CHECK-SPIRV: OpSwitch %[[#]] %[[#]] 0 %[[#]] 1 %[[#]] 2 %[[#]]
20
21define spir_kernel void @test_switch(i32 addrspace(1)* %res, i8 zeroext %val) {
22entry:
23  %res.addr = alloca i32 addrspace(1)*, align 4
24  %val.addr = alloca i8, align 1
25  store i32 addrspace(1)* %res, i32 addrspace(1)** %res.addr, align 4
26  store i8 %val, i8* %val.addr, align 1
27  %0 = load i8, i8* %val.addr, align 1
28  switch i8 %0, label %sw.epilog [
29    i8 0, label %sw.bb
30    i8 1, label %sw.bb1
31    i8 2, label %sw.bb2
32  ]
33
34sw.bb:                                            ; preds = %entry
35  %1 = load i32 addrspace(1)*, i32 addrspace(1)** %res.addr, align 4
36  store i32 1, i32 addrspace(1)* %1, align 4
37  br label %sw.epilog
38
39sw.bb1:                                           ; preds = %entry
40  %2 = load i32 addrspace(1)*, i32 addrspace(1)** %res.addr, align 4
41  store i32 2, i32 addrspace(1)* %2, align 4
42  br label %sw.epilog
43
44sw.bb2:                                           ; preds = %entry
45  %3 = load i32 addrspace(1)*, i32 addrspace(1)** %res.addr, align 4
46  store i32 3, i32 addrspace(1)* %3, align 4
47  br label %sw.epilog
48
49sw.epilog:                                        ; preds = %entry, %sw.bb2, %sw.bb1, %sw.bb
50  ret void
51}
52