1; RUN: llc -mtriple=sparcv9 <%s | FileCheck %s 2 3;; Ensures that inline-asm accepts and uses 'f' and 'e' register constraints. 4; CHECK-LABEL: faddd: 5; CHECK: faddd %f0, %f2, %f0 6define double @faddd(double, double) local_unnamed_addr #2 { 7entry: 8 %2 = tail call double asm sideeffect "faddd $1, $2, $0;", "=f,f,e"(double %0, double %1) #7 9 ret double %2 10} 11 12; CHECK-LABEL: faddq: 13; CHECK: faddq %f0, %f4, %f0 14define fp128 @faddq(fp128, fp128) local_unnamed_addr #2 { 15entry: 16 %2 = tail call fp128 asm sideeffect "faddq $1, $2, $0;", "=f,f,e"(fp128 %0, fp128 %1) #7 17 ret fp128 %2 18} 19 20;; Ensure that 'e' can indeed go in the high area, and 'f' cannot. 21; CHECK-LABEL: faddd_high: 22; CHECK: fmovd %f2, %f32 23; CHECK: fmovd %f0, %f2 24; CHECK: faddd %f2, %f32, %f2 25define double @faddd_high(double, double) local_unnamed_addr #2 { 26entry: 27 %2 = tail call double asm sideeffect "faddd $1, $2, $0;", "=f,f,e,~{d0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7}"(double %0, double %1) #7 28 ret double %2 29} 30 31; CHECK-LABEL: test_constraint_float_reg: 32; CHECK: fadds %f20, %f20, %f20 33; CHECK: faddd %f20, %f20, %f20 34; CHECK: faddq %f40, %f40, %f40 35define void @test_constraint_float_reg() { 36entry: 37 tail call void asm sideeffect "fadds $0,$1,$2", "{f20},{f20},{f20}"(float 6.0, float 7.0, float 8.0) 38 tail call void asm sideeffect "faddd $0,$1,$2", "{f20},{f20},{f20}"(double 9.0, double 10.0, double 11.0) 39 tail call void asm sideeffect "faddq $0,$1,$2", "{f40},{f40},{f40}"(fp128 0xL0, fp128 0xL0, fp128 0xL0) 40 ret void 41} 42 43;; Ensure that 64-bit immediates aren't truncated 44; CHECK-LABEL: test_large_immediate 45; CHECK: or %i0, %lo(4294967296), %i0 46define i64 @test_large_immediate(i64) { 47entry: 48 %1 = tail call i64 asm "or $0, %lo($1), $0", "=r,i,r"(i64 4294967296, i64 %0) 49 ret i64 %1 50} 51 52; Ensure that the input register value is not truncated to 32bit. 53; CHECK-LABEL: test_constraint_input_type 54; CHECK: ldx [%i0], %o0 55define void @test_constraint_input_type(ptr %arg1) { 56Entry: 57 %val = load i64, ptr %arg1 58 tail call void asm sideeffect "", "{o0}"(i64 %val) 59 ret void 60} 61