xref: /llvm-project/llvm/test/CodeGen/SPARC/hard-quad-float.ll (revision 586d5f91e6761747382b4f51df4acd340cd187e5)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=sparc64-unknown-linux-gnu | FileCheck %s --check-prefixes=SPARC64
3
4define fp128 @fpselect_softfloat(i32 signext %0, fp128 %1, fp128 %2) #0 {
5; SPARC64-LABEL: fpselect_softfloat:
6; SPARC64:         .cfi_startproc
7; SPARC64-NEXT:  ! %bb.0:
8; SPARC64-NEXT:    cmp %o0, 0
9; SPARC64-NEXT:    fmovd %f8, %f0
10; SPARC64-NEXT:    fmovd %f10, %f2
11; SPARC64-NEXT:    be %icc, .LBB0_2
12; SPARC64-NEXT:    nop
13; SPARC64-NEXT:  ! %bb.1:
14; SPARC64-NEXT:    fmovd %f4, %f0
15; SPARC64-NEXT:    fmovd %f6, %f2
16; SPARC64-NEXT:  .LBB0_2:
17; SPARC64-NEXT:    retl
18; SPARC64-NEXT:    nop
19  %a = icmp eq i32 %0, 0
20  %b = select i1 %a, fp128 %2, fp128 %1
21  ret fp128 %b
22}
23
24define fp128 @fpselect_hardfloat(i32 signext %0, fp128 %1, fp128 %2) #1 {
25; SPARC64-LABEL: fpselect_hardfloat:
26; SPARC64:         .cfi_startproc
27; SPARC64-NEXT:  ! %bb.0:
28; SPARC64-NEXT:    fmovq %f4, %f0
29; SPARC64-NEXT:    cmp %o0, 0
30; SPARC64-NEXT:    retl
31; SPARC64-NEXT:    fmovqe %icc, %f8, %f0
32  %a = icmp eq i32 %0, 0
33  %b = select i1 %a, fp128 %2, fp128 %1
34  ret fp128 %b
35}
36
37attributes #0 = { "target-features"="-hard-quad-float" }
38attributes #1 = { "target-features"="+hard-quad-float" }
39