xref: /llvm-project/llvm/test/CodeGen/SPARC/getpcx-rdpc.ll (revision 118d4234ac6d0893974d324cdb738a1e0255c08d)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -relocation-model=pic -mtriple=sparc | FileCheck --check-prefix=SPARC %s
3; RUN: llc < %s -relocation-model=pic -mtriple=sparcv9 | FileCheck --check-prefix=SPARC64 %s
4
5;; SPARC32 and SPARC64 for classic UltraSPARCs implement GETPCX
6;; with a fake `call`.
7;; All other SPARC64 targets implement it with `rd %pc, %o7`.
8;; Need to do the tests in separate files because apparently `tune-cpu`
9;; attribute applies to the entire file at once.
10
11@value = external global i32
12
13define i32 @testRdpc() nounwind #0 {
14; SPARC-LABEL: testRdpc:
15; SPARC:       ! %bb.0:
16; SPARC-NEXT:    save %sp, -96, %sp
17; SPARC-NEXT:  .Ltmp0:
18; SPARC-NEXT:    call .Ltmp1
19; SPARC-NEXT:  .Ltmp2:
20; SPARC-NEXT:    sethi %hi(_GLOBAL_OFFSET_TABLE_+(.Ltmp2-.Ltmp0)), %i0
21; SPARC-NEXT:  .Ltmp1:
22; SPARC-NEXT:    or %i0, %lo(_GLOBAL_OFFSET_TABLE_+(.Ltmp1-.Ltmp0)), %i0
23; SPARC-NEXT:    add %i0, %o7, %i0
24; SPARC-NEXT:    sethi %hi(value), %i1
25; SPARC-NEXT:    add %i1, %lo(value), %i1
26; SPARC-NEXT:    ld [%i0+%i1], %i0
27; SPARC-NEXT:    ld [%i0], %i0
28; SPARC-NEXT:    ret
29; SPARC-NEXT:    restore
30;
31; SPARC64-LABEL: testRdpc:
32; SPARC64:       ! %bb.0:
33; SPARC64-NEXT:    save %sp, -128, %sp
34; SPARC64-NEXT:  .Ltmp0:
35; SPARC64-NEXT:    rd %pc, %o7
36; SPARC64-NEXT:  .Ltmp2:
37; SPARC64-NEXT:    sethi %hi(_GLOBAL_OFFSET_TABLE_+(.Ltmp2-.Ltmp0)), %i0
38; SPARC64-NEXT:  .Ltmp1:
39; SPARC64-NEXT:    or %i0, %lo(_GLOBAL_OFFSET_TABLE_+(.Ltmp1-.Ltmp0)), %i0
40; SPARC64-NEXT:    add %i0, %o7, %i0
41; SPARC64-NEXT:    sethi %hi(value), %i1
42; SPARC64-NEXT:    add %i1, %lo(value), %i1
43; SPARC64-NEXT:    ldx [%i0+%i1], %i0
44; SPARC64-NEXT:    ld [%i0], %i0
45; SPARC64-NEXT:    ret
46; SPARC64-NEXT:    restore
47  %1 = load i32, ptr @value
48  ret i32 %1
49}
50
51attributes #0 = { "tune-cpu"="niagara" }
52