1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zfhmin < %s \ 3; RUN: | FileCheck --check-prefix=RV32IZFHMIN %s 4; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+zfhmin,+d < %s \ 5; RUN: | FileCheck --check-prefix=RV32IDZFHMIN %s 6; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zhinxmin < %s \ 7; RUN: | FileCheck --check-prefix=RV32IZHINXMIN %s 8; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zhinxmin,+zdinx < %s \ 9; RUN: | FileCheck --check-prefix=RV32IZDINXZHINXMIN %s 10; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+zfhmin < %s \ 11; RUN: | FileCheck --check-prefix=RV64IZFHMIN %s 12; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+zfhmin,+d < %s \ 13; RUN: | FileCheck --check-prefix=RV64IDZFHMIN %s 14; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zhinxmin < %s \ 15; RUN: | FileCheck --check-prefix=RV64IZHINXMIN %s 16; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zhinxmin,+zdinx < %s \ 17; RUN: | FileCheck --check-prefix=RV64IZDINXZHINXMIN %s 18 19define half @f16_positive_zero(ptr %pf) nounwind { 20; RV32IZFHMIN-LABEL: f16_positive_zero: 21; RV32IZFHMIN: # %bb.0: 22; RV32IZFHMIN-NEXT: fmv.h.x fa0, zero 23; RV32IZFHMIN-NEXT: ret 24; 25; RV32IDZFHMIN-LABEL: f16_positive_zero: 26; RV32IDZFHMIN: # %bb.0: 27; RV32IDZFHMIN-NEXT: fmv.h.x fa0, zero 28; RV32IDZFHMIN-NEXT: ret 29; 30; RV32IZHINXMIN-LABEL: f16_positive_zero: 31; RV32IZHINXMIN: # %bb.0: 32; RV32IZHINXMIN-NEXT: li a0, 0 33; RV32IZHINXMIN-NEXT: ret 34; 35; RV32IZDINXZHINXMIN-LABEL: f16_positive_zero: 36; RV32IZDINXZHINXMIN: # %bb.0: 37; RV32IZDINXZHINXMIN-NEXT: li a0, 0 38; RV32IZDINXZHINXMIN-NEXT: ret 39; 40; RV64IZFHMIN-LABEL: f16_positive_zero: 41; RV64IZFHMIN: # %bb.0: 42; RV64IZFHMIN-NEXT: fmv.h.x fa0, zero 43; RV64IZFHMIN-NEXT: ret 44; 45; RV64IDZFHMIN-LABEL: f16_positive_zero: 46; RV64IDZFHMIN: # %bb.0: 47; RV64IDZFHMIN-NEXT: fmv.h.x fa0, zero 48; RV64IDZFHMIN-NEXT: ret 49; 50; RV64IZHINXMIN-LABEL: f16_positive_zero: 51; RV64IZHINXMIN: # %bb.0: 52; RV64IZHINXMIN-NEXT: li a0, 0 53; RV64IZHINXMIN-NEXT: ret 54; 55; RV64IZDINXZHINXMIN-LABEL: f16_positive_zero: 56; RV64IZDINXZHINXMIN: # %bb.0: 57; RV64IZDINXZHINXMIN-NEXT: li a0, 0 58; RV64IZDINXZHINXMIN-NEXT: ret 59 ret half 0.0 60} 61 62define half @f16_negative_zero(ptr %pf) nounwind { 63; RV32IZFHMIN-LABEL: f16_negative_zero: 64; RV32IZFHMIN: # %bb.0: 65; RV32IZFHMIN-NEXT: lui a0, 1048568 66; RV32IZFHMIN-NEXT: fmv.h.x fa0, a0 67; RV32IZFHMIN-NEXT: ret 68; 69; RV32IDZFHMIN-LABEL: f16_negative_zero: 70; RV32IDZFHMIN: # %bb.0: 71; RV32IDZFHMIN-NEXT: lui a0, 1048568 72; RV32IDZFHMIN-NEXT: fmv.h.x fa0, a0 73; RV32IDZFHMIN-NEXT: ret 74; 75; RV32IZHINXMIN-LABEL: f16_negative_zero: 76; RV32IZHINXMIN: # %bb.0: 77; RV32IZHINXMIN-NEXT: lui a0, 1048568 78; RV32IZHINXMIN-NEXT: ret 79; 80; RV32IZDINXZHINXMIN-LABEL: f16_negative_zero: 81; RV32IZDINXZHINXMIN: # %bb.0: 82; RV32IZDINXZHINXMIN-NEXT: lui a0, 1048568 83; RV32IZDINXZHINXMIN-NEXT: ret 84; 85; RV64IZFHMIN-LABEL: f16_negative_zero: 86; RV64IZFHMIN: # %bb.0: 87; RV64IZFHMIN-NEXT: lui a0, 1048568 88; RV64IZFHMIN-NEXT: fmv.h.x fa0, a0 89; RV64IZFHMIN-NEXT: ret 90; 91; RV64IDZFHMIN-LABEL: f16_negative_zero: 92; RV64IDZFHMIN: # %bb.0: 93; RV64IDZFHMIN-NEXT: lui a0, 1048568 94; RV64IDZFHMIN-NEXT: fmv.h.x fa0, a0 95; RV64IDZFHMIN-NEXT: ret 96; 97; RV64IZHINXMIN-LABEL: f16_negative_zero: 98; RV64IZHINXMIN: # %bb.0: 99; RV64IZHINXMIN-NEXT: lui a0, 1048568 100; RV64IZHINXMIN-NEXT: ret 101; 102; RV64IZDINXZHINXMIN-LABEL: f16_negative_zero: 103; RV64IZDINXZHINXMIN: # %bb.0: 104; RV64IZDINXZHINXMIN-NEXT: lui a0, 1048568 105; RV64IZDINXZHINXMIN-NEXT: ret 106 ret half -0.0 107} 108