1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfhmin \ 3; RUN: -verify-machineinstrs -target-abi ilp32f | \ 4; RUN: FileCheck -check-prefix=RV32IZFHMIN %s 5; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfhmin \ 6; RUN: -verify-machineinstrs -target-abi lp64f | \ 7; RUN: FileCheck -check-prefix=RV64IZFHMIN %s 8; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \ 9; RUN: -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32d | \ 10; RUN: FileCheck -check-prefix=RV32IDZFHMIN %s 11; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \ 12; RUN: -mattr=+zfhmin -verify-machineinstrs -target-abi lp64d | \ 13; RUN: FileCheck -check-prefix=RV64IDZFHMIN %s 14; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zhinxmin \ 15; RUN: -verify-machineinstrs -target-abi ilp32 | \ 16; RUN: FileCheck -check-prefix=RV32IZHINXMIN %s 17; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zhinxmin \ 18; RUN: -verify-machineinstrs -target-abi lp64 | \ 19; RUN: FileCheck -check-prefix=RV64IZHINXMIN %s 20; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zdinx \ 21; RUN: -mattr=+zhinxmin -verify-machineinstrs -target-abi ilp32 | \ 22; RUN: FileCheck -check-prefix=RV32IZDINXZHINXMIN %s 23; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zdinx \ 24; RUN: -mattr=+zhinxmin -verify-machineinstrs -target-abi lp64 | \ 25; RUN: FileCheck -check-prefix=RV64IZDINXZHINXMIN %s 26 27; These intrinsics require half to be a legal type. 28 29declare iXLen @llvm.lrint.iXLen.f16(half) 30 31define iXLen @lrint_f16(half %a) nounwind { 32; RV32IZFHMIN-LABEL: lrint_f16: 33; RV32IZFHMIN: # %bb.0: 34; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0 35; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5 36; RV32IZFHMIN-NEXT: ret 37; 38; RV64IZFHMIN-LABEL: lrint_f16: 39; RV64IZFHMIN: # %bb.0: 40; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 41; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5 42; RV64IZFHMIN-NEXT: ret 43; 44; RV32IDZFHMIN-LABEL: lrint_f16: 45; RV32IDZFHMIN: # %bb.0: 46; RV32IDZFHMIN-NEXT: fcvt.s.h fa5, fa0 47; RV32IDZFHMIN-NEXT: fcvt.w.s a0, fa5 48; RV32IDZFHMIN-NEXT: ret 49; 50; RV64IDZFHMIN-LABEL: lrint_f16: 51; RV64IDZFHMIN: # %bb.0: 52; RV64IDZFHMIN-NEXT: fcvt.s.h fa5, fa0 53; RV64IDZFHMIN-NEXT: fcvt.l.s a0, fa5 54; RV64IDZFHMIN-NEXT: ret 55; 56; RV32IZHINXMIN-LABEL: lrint_f16: 57; RV32IZHINXMIN: # %bb.0: 58; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 59; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0 60; RV32IZHINXMIN-NEXT: ret 61; 62; RV64IZHINXMIN-LABEL: lrint_f16: 63; RV64IZHINXMIN: # %bb.0: 64; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 65; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0 66; RV64IZHINXMIN-NEXT: ret 67; 68; RV32IZDINXZHINXMIN-LABEL: lrint_f16: 69; RV32IZDINXZHINXMIN: # %bb.0: 70; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 71; RV32IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0 72; RV32IZDINXZHINXMIN-NEXT: ret 73; 74; RV64IZDINXZHINXMIN-LABEL: lrint_f16: 75; RV64IZDINXZHINXMIN: # %bb.0: 76; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 77; RV64IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0 78; RV64IZDINXZHINXMIN-NEXT: ret 79 %1 = call iXLen @llvm.lrint.iXLen.f16(half %a) 80 ret iXLen %1 81} 82 83declare iXLen @llvm.lround.iXLen.f16(half) 84 85define iXLen @lround_f16(half %a) nounwind { 86; RV32IZFHMIN-LABEL: lround_f16: 87; RV32IZFHMIN: # %bb.0: 88; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0 89; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm 90; RV32IZFHMIN-NEXT: ret 91; 92; RV64IZFHMIN-LABEL: lround_f16: 93; RV64IZFHMIN: # %bb.0: 94; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 95; RV64IZFHMIN-NEXT: fcvt.l.s a0, fa5, rmm 96; RV64IZFHMIN-NEXT: ret 97; 98; RV32IDZFHMIN-LABEL: lround_f16: 99; RV32IDZFHMIN: # %bb.0: 100; RV32IDZFHMIN-NEXT: fcvt.s.h fa5, fa0 101; RV32IDZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm 102; RV32IDZFHMIN-NEXT: ret 103; 104; RV64IDZFHMIN-LABEL: lround_f16: 105; RV64IDZFHMIN: # %bb.0: 106; RV64IDZFHMIN-NEXT: fcvt.s.h fa5, fa0 107; RV64IDZFHMIN-NEXT: fcvt.l.s a0, fa5, rmm 108; RV64IDZFHMIN-NEXT: ret 109; 110; RV32IZHINXMIN-LABEL: lround_f16: 111; RV32IZHINXMIN: # %bb.0: 112; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 113; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rmm 114; RV32IZHINXMIN-NEXT: ret 115; 116; RV64IZHINXMIN-LABEL: lround_f16: 117; RV64IZHINXMIN: # %bb.0: 118; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 119; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rmm 120; RV64IZHINXMIN-NEXT: ret 121; 122; RV32IZDINXZHINXMIN-LABEL: lround_f16: 123; RV32IZDINXZHINXMIN: # %bb.0: 124; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 125; RV32IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rmm 126; RV32IZDINXZHINXMIN-NEXT: ret 127; 128; RV64IZDINXZHINXMIN-LABEL: lround_f16: 129; RV64IZDINXZHINXMIN: # %bb.0: 130; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 131; RV64IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0, rmm 132; RV64IZDINXZHINXMIN-NEXT: ret 133 %1 = call iXLen @llvm.lround.iXLen.f16(half %a) 134 ret iXLen %1 135} 136 137define i32 @lround_i32_f16(half %a) nounwind { 138; RV32IZFHMIN-LABEL: lround_i32_f16: 139; RV32IZFHMIN: # %bb.0: 140; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0 141; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm 142; RV32IZFHMIN-NEXT: ret 143; 144; RV64IZFHMIN-LABEL: lround_i32_f16: 145; RV64IZFHMIN: # %bb.0: 146; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0 147; RV64IZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm 148; RV64IZFHMIN-NEXT: ret 149; 150; RV32IDZFHMIN-LABEL: lround_i32_f16: 151; RV32IDZFHMIN: # %bb.0: 152; RV32IDZFHMIN-NEXT: fcvt.s.h fa5, fa0 153; RV32IDZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm 154; RV32IDZFHMIN-NEXT: ret 155; 156; RV64IDZFHMIN-LABEL: lround_i32_f16: 157; RV64IDZFHMIN: # %bb.0: 158; RV64IDZFHMIN-NEXT: fcvt.s.h fa5, fa0 159; RV64IDZFHMIN-NEXT: fcvt.w.s a0, fa5, rmm 160; RV64IDZFHMIN-NEXT: ret 161; 162; RV32IZHINXMIN-LABEL: lround_i32_f16: 163; RV32IZHINXMIN: # %bb.0: 164; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0 165; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rmm 166; RV32IZHINXMIN-NEXT: ret 167; 168; RV64IZHINXMIN-LABEL: lround_i32_f16: 169; RV64IZHINXMIN: # %bb.0: 170; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0 171; RV64IZHINXMIN-NEXT: fcvt.w.s a0, a0, rmm 172; RV64IZHINXMIN-NEXT: ret 173; 174; RV32IZDINXZHINXMIN-LABEL: lround_i32_f16: 175; RV32IZDINXZHINXMIN: # %bb.0: 176; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 177; RV32IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rmm 178; RV32IZDINXZHINXMIN-NEXT: ret 179; 180; RV64IZDINXZHINXMIN-LABEL: lround_i32_f16: 181; RV64IZDINXZHINXMIN: # %bb.0: 182; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0 183; RV64IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rmm 184; RV64IZDINXZHINXMIN-NEXT: ret 185 %1 = call i32 @llvm.lround.i32.f16(half %a) 186 ret i32 %1 187} 188